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L7200 Datasheet(PDF) 35 Page - Intel Corporation |
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L7200 Datasheet(HTML) 35 Page - Intel Corporation |
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35 / 91 page ![]() Datasheet 35 Electrical Specifications NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of BCLK1. 3. Threshold Region is defined as a region entered about the crossing voltage in which the differential receiver switches. It includes input threshold hysteresis. 4. For Vin (Input Voltage) between 0 V and VH. 5. Cpad includes die capacitance only. No package parasitics are included. 6. ΔV CROSS is defined as the total variation of all crossing voltages as defined in note 2. Figure 4. Deeper Sleep VCC and ICC Loadline for Dual-core Low Voltage and Ultra Low Voltage Processor ICC-CORE max {Deeper Sleep} VCC-CORE [V] VCC-CORE nom {Deeper Sleep} +/-VCC-CORE Tolerance = VR St. Pt. Error 1/ VCC-CORE, DC min {Deeper Sleep} VCC-CORE, DC max {Deeper Sleep} VCC-CORE max {Deeper Sleep} VCC-CORE min {Deeper Sleep} 10 mV= RIPPLE ICC-CORE [A] 0 Slope = -2.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. Note 1/ Deeper Sleep VCC-CORE Set Point Error Tolerance is per below : Tolerance VCC-CORE VID Voltage Range ------------------------------ -------------------------------------------------------- +/- (VID*1.5%) VCC-CORE > 0.7500V +/- 11.5 mV 0.7500V < VCC-CORE < 0.5000V +/- 25 mV 0.5000V < VCC-CORE < 0.4125V |
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