R27 datasheet(150/487 Pages) RENESAS

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R8C/26 Group, R8C/27 Group

12. Interrupts

Rev.2.10

Sep 26, 2008

Page 131 of 453

REJ09B0278-0210

12.5

Timer RC Interrupt, Clock Synchronous Serial I/O with Chip Select

Interrupts, and I2C bus Interface Interrupt (Interrupts with Multiple Interrupt

Request Sources)

The timer RC interrupt, clock synchronous serial I/O with chip select interrupt, and I2C bus interface interrupt each

have multiple interrupt request sources. An interrupt request is generated by the logical OR of several interrupt

request factors and is reflected in the IR bit in the corresponding interrupt control register. Therefore, each of these

peripheral functions has its own interrupt request source status register (status register) and interrupt request source

enable register (enable register) to control the generation of interrupt requests (change the IR bit in the interrupt

control register). Table 12.9 lists the Registers Associated with Timer RC Interrupt, Clock Synchronous Serial I/O

with Chip Select Interrupt, and I2C bus Interface Interrupt and Figure 12.19 shows a Block Diagram of Timer RC

Interrupt.

Figure 12.19

Block Diagram of Timer RC Interrupt

Table 12.9

Registers Associated with Timer RC Interrupt, Clock Synchronous Serial I/O with

Chip Select Interrupt, and I2C bus Interface Interrupt

Status Register of

Interrupt Request Source

Enable Register of

Interrupt Request Source

Interrupt Control

Timer RC

TRCSR

TRCIER

TRCIC

Clock synchronous serial

I/O with chip select

SSSR

SSER

SSUIC

I2C bus interface

ICSR

ICIER

IICIC

Timer RC

interrupt request

(IR bit in TRCIC register)

IMFA bit

IMIEA bit

IMFB bit

IMIEB bit

IMFC bit

IMIEC bit

IMFD bit

IMIED bit

IMFA, IMFB, IMFC, IMFD, OVF: Bits in TRCSR register

IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRCIER register

OVF bit

OVIE bit

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