R27 datasheet(151/487 Pages) RENESAS

151 / 487 page

R8C/26 Group, R8C/27 Group

12. Interrupts

Rev.2.10

Sep 26, 2008

Page 132 of 453

REJ09B0278-0210

As with other maskable interrupts, the timer RC interrupt, clock synchronous serial I/O with chip select interrupt,

and I2C bus interface interrupt are controlled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL.

However, since each interrupt source is generated by a combination of multiple interrupt request sources, the

following differences from other maskable interrupts apply:

• When bits in the enable register corresponding to bits set to 1 in the status register are set to 1 (enable

interrupt), the IR bit in the interrupt control register is set to 1 (interrupt requested).

• When either bits in the status register or bits in the enable register corresponding to bits in the status register, or

both, are set to 0, the IR bit is set to 0 (interrupt not requested). Basically, even though the interrupt is not

acknowledged after the IR bit is set to 1, the interrupt request will not be maintained. Also, the IR bit is not set

to 0 even if 0 is written to the IR bit.

• Individual bits in the status register are not automatically set to 0 even if the interrupt is acknowledged.

Therefore, the IR bit is also not automatically set to 0 when the interrupt is acknowledged. Set each bit in the

status register to 0 in the interrupt routine. Refer to the status register figure for how to set individual bits in the

status register to 0.

• When multiple bits in the enable register are set to 1 and other request sources are generated after the IR bit is

set to 1, the IR bit remains 1.

• When multiple bits in the enable register are set to 1, determine by the status register which request source

causes an interrupt.

Refer to chapters of the individual peripheral functions (14.3 Timer RC, 16.2 Clock Synchronous Serial I/O with

Chip Select (SSU) and 16.3 I2C bus Interface) for the status register and enable register.

Refer to 12.1.6 Interrupt Control for the interrupt control register.

R27 Datasheet(PDF) 151 Page - Renesas Technology Corp