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R27 Datasheet(PDF) 166 Page - Renesas Technology Corp

Part # R27
Description  RENESAS 16-BIT SINGLE-CHIP MCU R8C FAMILY / R8C/2x SERIES
PDF  487 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R27 Datasheet(HTML) 166 Page - Renesas Technology Corp

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R8C/26 Group, R8C/27 Group
14. Timers
Rev.2.10
Sep 26, 2008
Page 147 of 453
REJ09B0278-0210
14.1.1.1
Timer Write Control during Count Operation
Timer RA has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each
consist of a reload register and a counter. When writing to the prescaler or timer, values are written to both the
reload register and counter.
However, values are transferred from the reload register to the counter of the prescaler in synchronization with
the count source. In addition, values are transferred from the reload register to the counter of the timer in
synchronization with prescaler underflows. Therefore, if the prescaler or timer is written to when count
operation is in progress, the counter value is not updated immediately after the WRITE instruction is executed.
Figure 14.5 shows an Operating Example of Timer RA when Counter Value is Rewritten during Count
Operation.
Figure 14.5
Operating Example of Timer RA when Counter Value is Rewritten during Count
Operation
Count source
Reloads register of
timer RA prescaler
IR bit in TRAIC
register
0
Counter of
timer RA prescaler
Reloads register of
timer RA
Counter of timer RA
Set 01h to the TRAPRE register and 25h to
the TRA register by a program.
After writing, the reload register is
written to at the first count source.
Reload at
second count
source
Reload at
underflow
After writing, the reload register is
written to at the first underflow.
Reload at the second underflow
The IR bit remains unchanged until underflow is
generated by a new value.
05h
04h
01h
00h
01h
00h
01h
00h
01h
00h
06h
New value (01h)
Previous value
New value (25h)
Previous value
03h
24h
02h
25h
The above applies under the following conditions.
Both bits TSTART and TCSTF in the TRACR register are set to 1 (During count).



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