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R28 Datasheet(PDF) 355 Page - Renesas Technology Corp |
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R28 Datasheet(HTML) 355 Page - Renesas Technology Corp |
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355 / 473 page  R8C/28 Group, R8C/29 Group 18. A/D Converter Rev.2.10 Sep 26, 2008 Page 336 of 441 REJ09B0279-0210 18.3 Sample and Hold When the SMP bit in the ADCON2 register is set to 1 (sample and hold function enabled), the A/D conversion rate per pin increases. The sample and hold function is available in all operating modes. Start A/D conversion after selecting whether the sample and hold circuit is to be used or not. Figure 18.8 shows a Timing Diagram of A/D Conversion. Figure 18.8 Timing Diagram of A/D Conversion 18.4 A/D Conversion Cycles Figure 18.9 shows the A/D Conversion Cycles. Figure 18.9 A/D Conversion Cycles Sampling time 4ø AD cycles Sample and hold disabled Conversion time of 1st bit 2nd bit Comparison time Sampling time 2.5ø AD cycles Comparison time Sampling time 2.5ø AD cycles Comparison time * Repeat until conversion ends Sampling time 4ø AD cycles Sample and hold enabled Conversion time of 1st bit 2nd bit Comparison time Comparison time Comparison time * Repeat until conversion ends Comparison time A/D Conversion Mode Without Sample & Hold Without Sample & Hold With Sample & Hold With Sample & Hold 8 bits 10 bits 8 bits 10 bits Conversion Time Comparison Time Comparison Time End process Sampling Time End process Conversion time at the 1st bit Sampling Time Conversion time at the 2nd bit and the follows 49 φAD 4 φAD 2.0 φAD 2.5 φAD 2.5 φAD 8.0 φAD 59 φAD 4 φAD 2.0 φAD 2.5 φAD 2.5 φAD 8.0 φAD 28 φAD 4 φAD 2.5 φAD 0.0 φAD 2.5 φAD 4.0 φAD 33 φAD 4 φAD 2.5 φAD 0.0 φAD 2.5 φAD 4.0 φAD |
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