TLE 7469

Data Sheet

13

Rev. 1.6, 2008-01-22

Since the regulator output current roughly rises linearly with time the discharge of the

capacitor can be calculated as follows:

dVC

The drop across the ESR calculates as:

dV

To prevent a reset the following relationship must be fullfilled:

dV

Example: Assuming a load current step of dI

22µF and a typical regulator reaction time under normal operating conditions of dt ~

25µs and for special dynamic load conditions, such as load step from very low base

load, a reaction time of dt ~ 75µs.

dV

So for the ESR we can allow

dV

The permissible ESR becomes:

ESR = dV

During design-in of the TLE7469 product family, special care needs to be taken with

regards to the regulators reaction time to sudden load current changes starting from very

low pre-load as well as cyclic load changes. The application note “TLE7x Voltage

Regulators - Application Note about Transient Response at ultra low quiescent current

Voltage Regulators” (see 3_cip05405.pdf) gives important hints for successful design-in

of the Voltage Regulators of the TLE7x family.

As a dual regulator the TLE 7469 for correct operation should be always supplied at both

input pins I1 and I2 out of one voltage supply. The dual voltage regulator with both inputs

accessible, offers the possibility to reduce the power dissipation in the package. This can

be achived by two different input voltages or a Drop Resistor* R

input pin I2 for the 2.6V output. If one of this options is chosen,care should be taken, to

apply the device as descibed under “Table 3: Operating Range”.

The reset output RO features an integrated pull-up resistor. Thus it can be directly

coupled to the microcontroller reset input.