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Product data sheet

Rev. 01 — 13 December 2005

7 of 13

Philips Semiconductors

PCK946

Low voltage 1 : 10 CMOS clock driver

At the load end the voltage will double, due to the near unity reflection coefficient, to 2.8 V.

It will then increment towards the quiescent 3.0 V in steps separated by one round trip

delay (in this case 4.0 ns).

Since this step is well above the threshold region it will not cause any false clock

triggering, however designers may be uncomfortable with unwanted reflections on the

line. To better match the impedances when driving multiple lines the situation in Figure 5

should be used. In this case the series terminating resistors are reduced such that when

the parallel combination is added to the output buffer impedance the line impedance is

perfectly matched.

SPICE level output buffer models are available for engineers who want to simulate their

specific interconnect schemes. In addition IV characteristics are in the process of being

generated to support the other board level simulators in general use.

Fig 4.

Single versus dual waveforms

7

Ω +36 Ω|| 36 Ω =50 Ω|| 50 Ω

25

Ω =25 Ω

Fig 5.

Optimized dual line termination

time (ns)

016

12

48

002aaa679

3.0

voltage

(V)

−0.5

0

1.0

2.0

IN

OutA

OutB

Zo = 50 Ω

002aaa680

Rs = 36 Ω

Zo = 50 Ω

Rs = 36 Ω

PCK946

OUTPUT

BUFFER

7

Ω

IN

Zo = 50 Ω

Ro