Analog Integrated Circuit Device Data

4

Freescale Semiconductor

33932

PIN CONNECTIONS

14-16

OUT4

Power

Output

H-Bridge Output 4

H-bridge B Source of high side MOSFET2 and drain of low side MOSFET2.

17,18,26-28

VPWRB

Power Input

Positive Power

Supply

These pins must be connected together physically as close as possible and

directly soldered down to a wide, thick, low resistance supply plane on the PCB.

19

CCPB

Analog

Output

Charge Pump

Capacitor

External reservoir capacitor connection for H-bridge B internal charge pump;

connected to VPWRB. Allowable values are 30 to 100 nF. Note: This capacitor

is required for the proper performance of the device.

20

IN4

Logic Input

Input 4

Logic input control of OUT4.

21

IN3

Logic Input

Input 3

Logic input control of OUT3.

22

SFB

Logic

Output -

Open Drain

Status Flag B

(Active Low)

H-bridge B open drain active LOW Status Flag output (requires an external pull-

23

D3

Logic Input

Disable Input 3

(Active High)

When D3 is logic HIGH, both OUT3 and OUT4 are tri-stated. Schmitt trigger

input with ~80

μA source so default condition = disabled.

24

FBB

Analog

Output

Feedback B

H-bridge B load current feedback output provides ground referenced 0.24% of

the high side output current. (Tie to GND through a resistor if not used.)

25

EN/D4

Logic Input

Enable Input

When EN/D4 is logic HIGH, H-bridge B is operational. When EN/D4 is logic

LOW, the H-bridge B outputs are tri-stated and H-bridge B is placed in Sleep

Mode. (logic input with ~80

μA sink so default condition = Sleep Mode.)

29-31

OUT3

Power

Output

H-Bridge Output 3

H-bridge B Source of high side MOSFET1 and drain of low side MOSFET1.

36-38

OUT2

Power

Output

H-Bridge Output 2

H-Bridge A source of high side MOSFET2 and drain of low side MOSFET2.

41

CCPA

Analog

Output

Charge Pump

Capacitor

External reservoir capacitor connection for H-bridge A internal charge pump;

connected to VPWRA. Allowable values are 30 to 100 nF. Note: This capacitor

is required for the proper performance of the device.

42

IN2

Logic Input

Input 2

Logic input control of OUT2.

43

IN1

Logic Input

Input 1

Logic input control of OUT1; e.g., when IN1 is logic HIGH, OUT1 is set to

VPWRA, and when IN1 is logic LOW, OUT1 is set to PGNDA. (Schmitt trigger

Input with ~80

μA source so default condition = OUT1 HIGH.)

44

SFA

Logic

Output -

Open Drain

Status Flag

(Active Low)

H-Bridge A open drain active LOW Status Flag output (requires an external

TAB

AGNDA

AGNDB

Analog

Ground

Analog Signal

Ground

The low-current analog signal ground must be connected to PGND via low-

impedance path (<<10 m

Ω, 0 Hz to 20 kHz). Exposed TAB is also the main

heatsinking path for the device.

Table 1. 33932 Pin Definitions (continued)

Pin

Pin Name

Pin

Function

Formal Name

Definition