ADSP-BF504 datasheet(66/80 Pages) AD

66 / 80 page

Rev. PrC

Page 66 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Preliminary Technical Data

required acquisition time for the next sampling instant at Point

B; therefore, the analog inputs are configured as differential for

that conversion.

The channels used for simultaneous conversions are selected via

the multiplexer address input pins, A0 to A2. The logic states of

these pins also need to be established prior to the acquisition

time; however, they may change during the conversion time

provided the mode is not changed. If the mode is changed from

fully differential to pseudo differential, for example, then the

acquisition time would start again from this point. The selected

input channels are decoded as shown in Table 51 (Analog Input

Type and Channel Selection).

The analog input range of the ADC can be selected as 0 V to

VREF or 0 V to 2 × VREF via the RANGE pin. This selection is

made in a similar fashion to that of the SGL/DIFF pin by setting

the logic state of the RANGE pin a time tacq prior to the falling

edge of CS. Subsequent to this, the logic level on this pin can be

altered after the third falling edge of ADSCLK. If this pin is tied

to a logic low, the analog input range selected is 0 V to VREF. If

this pin is tied to a logic high, the analog input range selected is

0 V to 2 × VREF.

Output Coding

The ADC output coding is set to either twos complement or

straight binary, depending on which analog input configuration

is selected for a conversion. Table 50 (ADC Output Coding)

shows which output coding scheme is used for each possible

analog input configuration.

Transfer Functions

The designed code transitions occur at successive integer LSB

values (1 LSB, 2 LSB, and so on). In single-ended mode, the LSB

size is VREF/4096 when the 0 V to VREF range is used, and the LSB

size is 2 × VREF/4096 when the 0 V to 2 × VREF range is used. In

differential mode, the LSB size is 2 × VREF /4096 when the 0 V to

VREF range is used, and the LSB size is 4 × VREF/4096 when the 0

V to 2 × VREF range is used. The ideal transfer characteristic for

the ADC when straight binary coding is output is shown in

Figure 84 (Straight Binary Transfer Characteristic), and the

ideal transfer characteristic for the ADC when twos comple-

ment coding is output is shown in Figure 85 (Twos

Complement Transfer Characteristic with VREF ± VREF Input

Range) (this is shown with the 2 × VREF range).

Figure 83. Selecting Differential or Single-Ended Configuration

ADSCLK

114

SGL/DIFF

tACQ

Table 50. ADC Output Coding

SGL/DIFF

RANGE

Output Coding

(Differential Input)

(0 V to VREF)

Twos complement

(Differential Input)

(0 V to 2 × VREF)

Twos complement

(Single-Ended Input)

(0 V to VREF)

Straight binary

(Single-Ended Input)

(0 V to2 × VREF)

Twos complement

(Pseudo-Differential Input)

(0 V to VREF)

Straight binary

(Pseudo-Differential Input)

(0 V to 2 × VREF)

Twos complement

Table 51. Analog Input Type and Channel Selection

ADC A

ADC B

SGL/DIFF

VIN+

VIN–

VIN+

VIN–

Comment

000VA1

AGND

VB1

AGND

Single ended

001VA2

AGND

VB2

AGND

Single ended

010VA3

AGND

VB3

AGND

Single ended

011VA4

AGND

VB4

AGND

Single ended

100VA5

AGND

VB5

AGND

Single ended

101VA6

AGND

VB6

AGND

Single ended

000VA1

VA2

VB1

VB2

Fully differential

001VA1

VA2

VB1

VB2

Pseudo differential

010VA3

VA4

VB3

VB4

Fully differential

011VA3

VA4

VB3

VB4

Pseudo differential

100VA5

VA6

VB5

VB6

Fully differential

101VA5

VA6

VB5

VB6

Pseudo differential

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