ADSP-BF504 datasheet(12/80 Pages) AD

12 / 80 page

Rev. PrC

Page 12 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Preliminary Technical Data

The PPI supports a variety of general-purpose and ITU-R 656

modes of operation. In general-purpose mode, the PPI provides

half-duplex, bidirectional data transfer with up to 16 bits of

data. Up to three frame synchronization signals are also pro-

vided. In ITU-R 656 mode, the PPI provides half-duplex

bidirectional transfer of 8- or 10-bit video data. Additionally,

on-chip decode of embedded start-of-line (SOL) and start-of-

field (SOF) preamble packets is supported.

General-Purpose Mode Descriptions

The general-purpose modes of the PPI are intended to suit a

wide variety of data capture and transmission applications.

Three distinct submodes are supported:

• Input mode – Frame syncs and data are inputs into the PPI.

• Frame capture mode – Frame syncs are outputs from the

PPI, but data are inputs.

• Output mode – Frame syncs and data are outputs from the

PPI.

Input Mode

Input mode is intended for ADC applications, as well as video

communication with hardware signaling. In its simplest form,

PPI_FS1 is an external frame sync input that controls when to

read data. The PPI_DELAY MMR allows for a delay (in

PPI_CLK cycles) between reception of this frame sync and the

initiation of data reads. The number of input data samples is

user programmable and defined by the contents of the

PPI_COUNT register. The PPI supports 8-bit and 10-bit

through 16-bit data, programmable in the PPI_CONTROL

Frame Capture Mode

Frame capture mode allows the video source(s) to act as a slave

(for frame capture for example). The ADSP-BF50x processors

control when to read from the video source(s). PPI_FS1 is an

HSYNC output and PPI_FS2 is a VSYNC output.

Output Mode

Output mode is used for transmitting video or other data with

up to three output frame syncs. Typically, a single frame sync is

appropriate for data converter applications, whereas two or

three frame syncs could be used for sending video with hard-

ware signaling.

ITU-R 656 Mode Descriptions

The ITU-R 656 modes of the PPI are intended to suit a wide

variety of video capture, processing, and transmission applica-

tions. Three distinct submodes are supported:

• Active video only mode

• Vertical blanking only mode

• Entire field mode

Active Video Mode

Active video only mode is used when only the active video por-

tion of a field is of interest and not any of the blanking intervals.

The PPI does not read in any data between the end of active

video (EAV) and start of active video (SAV) preamble symbols,

or any data present during the vertical blanking intervals. In this

mode, the control byte sequences are not stored to memory;

they are filtered by the PPI. After synchronizing to the start of

Field 1, the PPI ignores incoming samples until it sees an SAV

code. The user specifies the number of active video lines per

frame (in PPI_COUNT register).

Vertical Blanking Interval Mode

In this mode, the PPI only transfers vertical blanking interval

(VBI) data.

Entire Field Mode

In this mode, the entire incoming bit stream is read in through

the PPI. This includes active video, control preamble sequences,

and ancillary data that may be embedded in horizontal and ver-

tical blanking intervals. Data transfer starts immediately after

synchronization to Field 1. Data is transferred to or from the

synchronous channels through eight DMA engines that work

autonomously from the processor core.

RSI INTERFACE

The removable storage interface (RSI) controller acts as the host

interface for multimedia cards (MMC), secure digital memory

cards (SD), secure digital input/output cards (SDIO), and CE-

ATA hard disk drives. The following list describes the main fea-

tures of the RSI controller.

• Support for a single MMC, SD memory, SDIO card or CE-

ATA hard disk drive

• Support for 1-bit and 4-bit SD modes

• Support for 1-bit, 4-bit, and 8-bit MMC modes

• Support for 4-bit and 8-bit CE-ATA hard disk drives

• A ten-signal external interface with clock, command, and

up to eight data lines

• Card detection using one of the data signals

• Card interface clock generation from SCLK

• SDIO interrupt and read wait features

• CE-ATA command completion signal recognition and

disable

CONTROLLER AREA NETWORK (CAN) INTERFACE

The ADSP-BF50x processors provide a CAN controller that is a

communication controller implementing the Controller Area

Network (CAN) V2.0B protocol. This protocol is an asynchro-

nous communications protocol used in both industrial and

automotive control systems. CAN is well suited for control

applications due to its capability to communicate reliably over a

network since the protocol incorporates CRC checking, message

error tracking, and fault node confinement.

The CAN controller is based on a 32-entry mailbox RAM and

supports both the standard and extended identifier (ID) mes-

sage formats specified in the CAN protocol specification,

revision 2.0, part B.

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