ADSP-BF504 datasheet(11/80 Pages) AD

11 / 80 page

Preliminary Technical Data

Rev. PrC

Page 11 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

• Companding in hardware – Each SPORT can perform

A-law or μ-law companding according to ITU recommen-

dation G.711. Companding can be selected on the transmit

and/or receive channel of the SPORT without

additional latencies.

• DMA operations with single-cycle overhead – Each SPORT

can automatically receive and transmit multiple buffers of

memory data. The processor can link or chain sequences of

DMA transfers between a SPORT and memory.

• Interrupts – Each transmit and receive port generates an

interrupt upon completing the transfer of a data word or

after transferring an entire data buffer, or buffers,

through DMA.

• Multichannel capability – Each SPORT supports 128 chan-

nels out of a 1024-channel window and is compatible with

the H.100, H.110, MVIP-90, and HMVIP standards.

SERIAL PERIPHERAL INTERFACE (SPI) PORTS

The ADSP-BF50x processors have two SPI-compatible ports

that enable the processor to communicate with multiple SPI-

compatible devices.

The SPI interface uses three pins for transferring data: two data

pins MOSI (Master Output-Slave Input) and MISO (Master

Input-Slave Output) and a clock pin, serial clock (SCK). An SPI

chip select input pin (SPIx_SS) lets other SPI devices select the

processor, and three SPI chip select output pins (SPIx_SEL3–1)

let the processor select other SPI devices. The SPI select pins are

reconfigured general-purpose I/O pins. Using these pins, the

SPI port provides a full-duplex, synchronous serial interface,

which supports both master/slave modes and multimaster

environments.

The SPI port’s baud rate and clock phase/polarities are pro-

grammable, and it has an integrated DMA channel,

configurable to support transmit or receive data streams. The

SPI’s DMA channel can only service unidirectional accesses at

any given time.

The SPI port’s clock rate is calculated as:

Where the 16-bit SPI_BAUD register contains a value of 2

to 65,535.

During transfers, the SPI port simultaneously transmits and

receives by serially shifting data in and out on its two serial data

lines. The serial clock line synchronizes the shifting and sam-

pling of data on the two serial data lines.

UART PORTS (UARTS)

The ADSP-BF50x Blackfin processors provide two full-duplex

universal asynchronous receiver/transmitter (UART) ports.

Each UART port provides a simplified UART interface to other

peripherals or hosts, enabling full-duplex, DMA-supported,

asynchronous transfers of serial data. A UART port includes

support for five to eight data bits, one or two stop bits, and

none, even, or odd parity. Each UART port supports two modes

of operation:

• PIO (programmed I/O). The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

• DMA (direct memory access). The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. Each UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates. Flexi-

ble interrupt timing options are available on the transmit

side.

Each UART port’s baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable:

• Supporting bit rates ranging from (fSCLK/1,048,576) to

(fSCLK) bits per second.

• Supporting data formats from 7 to 12 bits per frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

The UART port’s clock rate is calculated as

Where the 16-bit UART divisor comes from the UARTx_DLH

significant eight bits), and the EDBO is a bit in the

UARTx_GCTL register.

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

The UARTs feature a pair of UAx_RTS (request to send) and

UAx_CTS (clear to send) signals for hardware flow purposes.

The transmitter hardware is automatically prevented from

sending further data when the UAx_CTS input is de-asserted.

The receiver can automatically de-assert its

UAx_RTS output when the enhanced receive FIFO exceeds a

certain high-water level. The capabilities of the UARTs are fur-

ther extended with support for the Infrared Data Association

(IrDA®) Serial Infrared Physical Layer Link Specification (SIR)

protocol.

PARALLEL PERIPHERAL INTERFACE (PPI)

The processor provides a parallel peripheral interface (PPI) that

can connect directly to parallel A/D and D/A converters, video

encoders and decoders, and other general-purpose peripherals.

The PPI consists of a dedicated input clock pin, up to three

frame synchronization pins, and up to 16 data pins. The input

clock supports parallel data rates up to half the system clock rate

and the synchronization signals can be configured as either

inputs or outputs.

SPI Clock Rate

SCLK

SPI_BAUD

------------------------------------

UART Clock Rate

fSCLK

1EDBO

–

()

UART_Divisor

------------------------------------------------------------------------

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