ADSP-BF504 datasheet(15/80 Pages) AD

15 / 80 page

Preliminary Technical Data

Rev. PrC

Page 15 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

where the variables in the equations are:

fCCLKNOM is the nominal core clock frequency

fCCLKRED is the reduced core clock frequency

VDDINTNOM is the nominal internal supply voltage

VDDINTRED is the reduced internal supply voltage

TNOM is the duration running at fCCLKNOM

TRED is the duration running at fCCLKRED

ADSP-BF50X VOLTAGE REGULATION

The ADSP-BF50x processors require an external voltage regula-

tor to power the VDDINT domain. To reduce standby power

consumption, the external voltage regulator can be signaled

through EXT_WAKE to remove power from the processor core.

This signal is high-true for power-up and may be connected

directly to the low-true shut-down input of many common

regulators.

While in the hibernate state, all external supplies (VDDEXT,

VDDFLASH) can still be applied, eliminating the need for external

buffers. The external voltage regulator can be activated from

this power down state by asserting the RESET pin, which then

initiates a boot sequence. EXT_WAKE indicates a wakeup to

the external voltage regulator.

The power good (PG) input signal allows the processor to start

only after the internal voltage has reached a chosen level. In this

way, the startup time of the external regulator is detected after

hibernation. For a complete description of the power good

functionality, refer to the ADSP-BF50x Blackfin Processor Hard-

ware Reference.

CLOCK SIGNALS

The processor can be clocked by an external crystal, a sine wave

input, or a buffered, shaped clock derived from an external

clock oscillator.

If an external clock is used, it should be a TTL-compatible signal

and must not be halted, changed, or operated below the speci-

fied frequency during normal operation. This signal is

connected to the processor’s CLKIN pin. When an external

clock is used, the XTAL pin must be left unconnected.

Alternatively, because the processor includes an on-chip oscilla-

tor circuit, an external crystal may be used. For fundamental

frequency operation, use the circuit shown in Figure 4. A paral-

lel-resonant, fundamental frequency, microprocessor-grade

crystal is connected across the CLKIN and XTAL pins. The on-

chip resistance between CLKIN and the XTAL pin is in the

500 k

Ω range. Further parallel resistors are typically not recom-

mended. The two capacitors and the series resistor shown in

Figure 4 fine tune phase and amplitude of the sine frequency.

The capacitor and resistor values shown in Figure 4 are typical

values only. The capacitor values are dependent upon the crystal

manufacturers’ load capacitance recommendations and the PCB

physical layout. The resistor value depends on the drive level

specified by the crystal manufacturer. The user should verify the

customized values based on careful investigations on multiple

devices over temperature range.

A third-overtone crystal can be used for frequencies above 25

MHz. The circuit is then modified to ensure crystal operation

only at the third overtone, by adding a tuned inductor circuit as

shown in Figure 4. A design procedure for third-overtone oper-

ation is discussed in detail in application note (EE-168) Using

Third Overtone Crystals with the ADSP-218x DSP on the Analog

Devices website (www.analog.com)—use site search on

“EE-168.”

The Blackfin core runs at a different clock rate than the on-chip

peripherals. As shown in Figure 5, the core clock (CCLK) and

system peripheral clock (SCLK) are derived from the input

clock (CLKIN) signal. An on-chip PLL is capable of multiplying

the CLKIN signal by a programmable multiplication factor

(bounded by specified minimum and maximum VCO frequen-

cies). The default multiplier is 6×, but it can be modified by a

software instruction sequence.

On-the-fly frequency changes can be effected by simply writing

to the PLL_DIV register. The maximum allowed CCLK and

SCLK rates depend on the applied voltages VDDINT and VDDEXT;

the VCO is always permitted to run up to the CCLK frequency

specified by the part’s speed grade. The EXTCLK pin can be

configured to output either the SCLK frequency or the input

buffered CLKIN frequency, called CLKBUF. When configured

to output SCLK (CLKOUT), the EXTCLK pin acts as a refer-

ence signal in many timing specifications. While active by

default, it can be disabled using the EBIU_AMGCTL register.

% Power Savings

Power Savings Factor

–

() 100%

Figure 4. External Crystal Connections

CLKIN

CLKOUT (SCLK)

XTAL

SELECT

CLKBUF

TO PLL CIRCUITRY

FOR OVERTONE

OPERATION ONLY:

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING

ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR

FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE

OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED

RESISTOR VALUE SHOULD BE REDUCED TO 0

18 pF *

330

BLACKFIN

560

EXTCLK

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