ADSP-BF504 datasheet(14/80 Pages) AD

14 / 80 page

Rev. PrC

Page 14 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Preliminary Technical Data

In the active mode, it is possible to disable the control input to

the PLL by setting the PLL_OFF bit in the PLL control register.

This register can be accessed with a user-callable routine in the

on-chip ROM called bfrom_SysControl(). If disabled, the PLL

control input must be re-enabled before transitioning to the

full-on or sleep modes.

For more information about PLL controls, see the “Dynamic

Power Management” chapter in the ADSP-BF50x Blackfin Pro-

cessor Hardware Reference.

Sleep Operating Mode—High Dynamic Power Savings

The sleep mode reduces dynamic power dissipation by disabling

the clock to the processor core (CCLK). The PLL and system

clock (SCLK), however, continue to operate in this mode. Typi-

cally, an external event wakes up the processor. When in the

sleep mode, asserting a wakeup enabled in the SIC_IWRx regis-

ters causes the processor to sense the value of the BYPASS bit in

the PLL control register (PLL_CTL). If BYPASS is disabled, the

processor transitions to the full on mode. If BYPASS is enabled,

the processor transitions to the active mode.

DMA accesses to L1 memory are not supported in sleep mode.

Deep Sleep Operating Mode—Maximum Dynamic Power

Savings

The deep sleep mode maximizes dynamic power savings by dis-

abling the clocks to the processor core (CCLK) and to all

synchronous peripherals (SCLK). Asynchronous peripherals

may still be running but cannot access internal resources or

external memory. This powered-down mode can only be exited

by assertion of the reset pin (RESET). Assertion of RESET while

in deep sleep mode causes the processor to transition to the full

on mode.

Hibernate State—Maximum Static Power Savings

The hibernate state maximizes static power savings by disabling

the voltage and clocks to the processor core (CCLK) and to all of

the peripherals (SCLK). This setting sets the internal power sup-

ply voltage (VDDINT) to 0 V to provide the lowest static power

dissipation. Any critical information stored internally (for

example, memory contents, register contents, and other infor-

mation) must be written to a non-volatile storage device prior to

removing power if the processor state is to be preserved.

Writing 0 to the HIBERNATE bit causes EXT_WAKE to transi-

tion low, which can be used to signal an external voltage

regulator to shut down.

Since VDDEXT can still be supplied in this mode, all of the exter-

nal pins three-state, unless otherwise specified. This allows

other devices that may be connected to the processor to still

have power applied without drawing unwanted current.

The processor can be woken up by asserting the RESET pin. All

hibernate wakeup events initiate the hardware reset sequence.

Individual sources are enabled by the VR_CTL register. The

EXT_WAKE signal indicates the occurrence of a wakeup event.

As long as VDDEXT is applied, the VR_CTL register maintains its

state during hibernation. All other internal registers and memo-

ries, however, lose their content in the hibernate state.

Power Savings

As shown in Table 5, the processor supports three different

power domains, which maximizes flexibility while maintaining

compliance with industry standards and conventions. By isolat-

ing the internal logic of the processor into its own power

domain, separate from other I/O, the processor can take advan-

tage of dynamic power management without affecting the other

I/O devices. There are no sequencing requirements for the vari-

ous power domains, but all domains must be powered

according to the appropriate Processor — Specifications table

for processor operating conditions; even if the feature/periph-

eral is not used.

The dynamic power management feature of the processor

allows both the processor’s input voltage (VDDINT) and clock fre-

quency (fCCLK) to be dynamically controlled.

The power dissipated by a processor is largely a function of its

clock frequency and the square of the operating voltage. For

example, reducing the clock frequency by 25% results in a 25%

reduction in dynamic power dissipation, while reducing the

voltage by 25% reduces dynamic power dissipation by more

than 40%. Further, these power savings are additive, in that if

the clock frequency and supply voltage are both reduced, the

power savings can be dramatic, as shown in the following

equations.

Table 4. Power Settings

Mode/State PLL

PLL

Bypassed

Core

Clock

(CCLK)

System

Clock

(SCLK)

Core

Power

Full On

Enabled

Enabled Enabled On

Active

Enabled/

Disabled

Yes

Enabled Enabled On

Sleep

Enabled

—

Disabled Enabled On

Deep Sleep

Disabled —

Disabled Disabled On

Hibernate

Disabled —

Disabled Disabled Off

Table 5. Power Domains

Power Domain

Power Supply

All internal logic, except Memory

VDDINT

Flash Memory

VDDFLASH

All other I/O

VDDEXT

ADC digital supply1 (Logic, I/O)

1 On ADSP-BF506F processor only.

DVDD, VDRIVE

ADC analog supply1

AVDD

Power Savings Factor

fCCLKRED

fCCLKNOM

--------------------------

VDDINTRED

VDDINTNOM

--------------------------------





TRED

TNOM

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







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