SC410 datasheet(16/26 Pages) SEMTECH

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SC410

Applications Information (continued)

PGOOD will transition low if the V

pin exceeds +20% of

nominal, which is also the over-voltage shutdown thresh-

old (900mV).

Output Over-Voltage Protection

OVP (Over-Voltage Protection) becomes active as soon as

the device is enabled. The threshold is set at 750mV + 20%

(900mV). When V

exceeds the OVP threshold, DL latches

high and the low-side MOSFET is turned on. DL remains

high and the controller remains off, until the EN input is

toggled or V

is cycled. There is a 5μs delay built into the

OVP detector to prevent false transitions. PGOOD is also

low after an OVP event.

Output Under-Voltage Protection

When V

falls to 75% of its nominal voltage (falls to

562.5mV) for eight consecutive clock cycles, the switcher

is shut off and the DH and DL drives are pulled low to turn

off the MOSFETs. The controller stays off until EN is toggled

or V

is cycled.

Over-Temperature Protection

If the temperature rises to 145°C the device will latch off.

The device can be activated after the temperature is

reduced below 145°C by cycling the EN pin.

LDO UVLO, and POR

UVLO (Under-Voltage Lock-Out) circuitry inhibits switch-

ing and tri-states the power FETs until V

LDO

rises above

4.0V. An internal POR (Power-On Reset) occurs when V

LDO

exceeds 4.0V, which resets the fault latch and soft start

counter to begin the soft start cycle. The SC410 then

begins a soft start cycle. The PWM will shut off if V

LDO

falls

below 3.7V.

Internal LDO Regulator

The SC410 has an internal regulator that supplies the bias

voltage for the PWM controller. This LDO can also supply

an additional external current for an external load through

the LDO pin.

When activated, the LDO checks the status of the

following signals to ensure proper operation can be

maintained.

EN pin

LDO

output voltage

VIN input voltage

While the EN pin is above 0.5V, the LDO will be activated.

While the V

LDO

output voltage remains below 4V (80% of

the final LDO voltage), the LDO short-cicuit protection is

enabled and limits the current to about 35mA. After the

LDO

exceeds 4.0V, then the LDO operates in its normal

regulation mode where the current is limited to about

100mA.

80% of VLDO Final

VLDO Final

Sort-circuit Protection @ ~35mA

Voltage regulating with

~100mA current limit

Figure 8 — LDO Start-Up

Design Procedure

When designing a switch mode supply the input voltage

range, load current, switching frequency, and inductor

ripple current must be specified.

The maximum input voltage (V

INMAX

) is the highest speci-

fied input voltage. The minimum input voltage ( V

INMIN

) is

determined by the lowest input voltage after evaluating

the voltage drops due to connectors, fuses, switches, and

PCB traces.

The following parameters define the design.

Nominal output voltage (V

OUT

)

Static or DC output tolerance

Transient response

Maximum load current (I

OUT

)

The two values of load current to evaluate are continuous

load current and peak load current. Continuous load

current relates to thermal stresses which drive the selec-

tion of the inductor and input capacitors. Peak load current

determines instantaneous component stresses and filter-

ing requirements such as inductor saturation, output

capacitors, and design of the current limit circuit.

•

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