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R5F52108ADFF Datasheet(PDF) 33 Page - Renesas Technology Corp |
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R5F52108ADFF Datasheet(HTML) 33 Page - Renesas Technology Corp |
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33 / 92 page ![]() R01DS0041EJ0050 Rev.0.50 Page 33 of 90 Apr 15, 2011 RX210 Group 2. CPU Under development Preliminary document Specifications in this document are tentative and subject to change. 2.2.2.6 Backup PSW (BPSW) The backup PSW (BPSW) is provided to speed up response to interrupts. After a fast interrupt has been generated, the contents of the processor status word (PSW) are saved in the BPSW. The allocation of bits in the BPSW corresponds to that in the PSW. 2.2.2.7 Fast Interrupt Vector Register (FINTV) The fast interrupt vector register (FINTV) is provided to speed up response to interrupts. The FINTV register specifies a branch destination address when a fast interrupt has been generated. 2.2.3 Register Associated with DSP Instructions 2.2.3.1 Accumulator (ACC) The accumulator (ACC) is a 64-bit register used for DSP instructions. The accumulator is also used for the multiply and multiply-and-accumulate instructions; EMUL, EMULU, MUL, and RMPA, in which case the prior value in the accumulator is modified by execution of the instruction. Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The MVTACHI and MVTACLO instructions write data to the higher-order 32 bits (bits 63 to 32) and the lower-order 32 bits (bits 31 to 0), respectively. Use the MVFACHI and MVFACMI instructions for reading data from the accumulator. The MVFACHI and MVFACMI instructions read data from the higher-order 32 bits (bits 63 to 32) and the middle 32 bits (bits 47 to 16), respectively. b31 b0 Value after reset: Undefined b31 b0 Value after reset: Undefined Range for reading by MVFACMI b63 b48 b47 b32 b31 b16 b15 b0 Range for reading and writing by MVTACHI and MVFACHI Range for writing by MVTACLO Value after reset: Undefined |
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