R5F52108ADFF datasheet(8/92 Pages) RENESAS

8 / 92 page

R01DS0041EJ0050 Rev.0.50

Page 8 of 90

Apr 15, 2011

RX210 Group

1. Overview

Under development Preliminary document

Specifications in this document are tentative and subject to change.

1.3

Block Diagram

Figure 1.2 shows a block diagram.

Figure 1.2

Block Diagram

External bus

BSC

ICU:

Interrupt control unit

DTC:

Data transfer controller

DMACA: DMA controller

BSC:

Bus controller

WDT:

Watchdog timer

IWDT:

Independent watchdog timer

ELC:

Event link controller

CRC:

CRC (cyclic redundancy check) calculator

SCI:

Serial communications interface

RSPI: Serial peripheral interface

RIIC:

2C bus interface

MTU2: Multi-function timer pulse unit 2

POE2: Port output enable 2

TMR:

8-bit timer

CMT:

Compare match timer

RTC:

Realtime clock

DOC: Data operation circuit

CAC:

Clock-frequency accuracy measuring circuit

Clock

generation

circuit

RX CPU

RAM

ROM

Port 0

Port 1

Port 2

Port 3

Port 4

10-bit D/A converter × 2 channels

Temperature sensor

RIIC × 1 channel

DOC

SCIc × 6 channels

WDT

E2 data flash

CRC

ELC

RTC

MTU2 × 6 channels

12-bit A/D converter × 16 channels

CMT x 2 channels (unit 1)

CMT x 2 channels (unit 0)

TMR x 2 channels (unit 1)

TMR × 2 channels (unit 0)

RSPI × 1 channel

DTC

DMACA × 4

channels

ICU

CAC

SCId × 1 channel

Port 5

Port A

Port B

Port C

Port D

Port E

Port H

Port J

POE2

IWDT

Comparator B × 2 channels

Comparator A × 2 channels

R5F52108ADFF Datasheet(PDF) 8 Page - Renesas Technology Corp

R5F52108ADFF Datasheet(HTML) 8 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

Datasheet Download

Link URL