| Electronic Components Datasheet Search |
|
M68HC11KA Datasheet(PDF) 49 Page - Motorola, Inc |
|
|
|||||||||||||||||||||||||||||
M68HC11KA Datasheet(HTML) 49 Page - Motorola, Inc |
|
49 / 68 page ![]() MC68HC11KA4 MOTOROLA MC68HC11KA4TS/D 49 Pins AVDD and AVSS provide the supply voltage to the digital portion of the A/D converter. Pins VRH and VRL provide the reference supply voltage inputs. A multiplexer allows the single A/D converter to select one of 16 analog input signals. Refer to the A/D converter channel assignment bits CD–CA description. The A/D converter control logic implements automatic conversion sequences on a selected channel four times or on a group of four channels once each. A write to the ADCTL register initiates conversions and, if made while a conversion is in process, a write to ADCTL also halts a conversion operation in progress. When the MULT bit is zero, the A/D converter system is configured to perform four consecutive conver- sions on the single channel specified by the four channel-select bits (CD–CA). When the MULT bit is one, the A/D system is configured to perform conversions on each channel in the group of four channels specified by the CD and CC channel select bits. Refer to Table 8. When the SCAN bit is zero, four conversions are performed in the desired channel group, once each, to fill the four result registers. When SCAN is one, conversions continue channel-by-channel in the de- sired group with the result registers being updated continually as new data becomes available. Figure 15 Timing Diagram for a Sequence of Four A/D Conversions Figure 16 Electrical Model of an Analog Input Pin (Sample Mode) 0 32 64 96 128 — E CYCLES SAMPLE ANALOG INPUT SUCCESSIVE APPROXIMATION SEQUENCE MSB 4 CYCLES BIT 6 2 CYC BIT 5 2 CYC BIT 4 2 CYC BIT 3 2 CYC BIT 2 2 CYC BIT 1 2 CYC LSB 2 CYC 2 CYC END CONVERT FIRST CHANNEL, UPDATE ADR1 CONVERT SECOND CHANNEL, UPDATE ADR2 CONVERT THIRD CHANNEL, UPDATE ADR3 CONVERT FOURTH CHANNEL, UPDATE ADR4 12 E CYCLES E CLOCK A/D CONVERSION TIM DIFFUSION/POLY < 2 pF COUPLER 400 nA JUNCTION LEAKAGE + ~20V – ~0.7V * * THIS ANALOG SWITCH IS CLOSED ONLY DURING THE 12-CYCLE SAMPLE TIME. VRL INPUT + ~12V – ~0.7V PROTECTION DEVICE ≤ 4 KΩ DUMMY N-CHANNEL OUTPUT DEVICE ANALOG INPUT PIN ~ 20 pF DAC CAPACITANCE ANALOG INPUT PIN |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |