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M68HC11KA Datasheet(PDF) 29 Page - Motorola, Inc

Part # M68HC11KA
Description  8-Bit Microcontroller
PDF  68 Pages
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Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

M68HC11KA Datasheet(HTML) 29 Page - Motorola, Inc

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MC68HC11KA4
MOTOROLA
MC68HC11KA4TS/D
29
PSEL[4:0] — Priority Select Bits [4:0]
Can be written only while bit I in the CCR is set (interrupts disabled). These bits select one interrupt
source to be elevated above all other I-bit related sources.
CONFIG is made up of EEPROM cells and static latches. The operation of the MCU is controlled directly
by these latches and not the actual EEPROM byte. When programming the CONFIG register, the EE-
PROM byte is being accessed. When the CONFIG register is being read, the static latches are being
accessed.
These bits can be read at any time. The value read is the one latched into the register from the EE-
PROM cells during the last reset sequence. A new value programmed into this register cannot be read
until after a subsequent reset sequence. Unused bits always read as ones.
If SMOD = 1, CONFIG bits can be written at any time. If SMOD = 0 CONFIG bits can only be written
using the EEPROM programming sequence, and are neither readable nor active until latched via the
next reset.
ROMAD — ROM/EPROM Mapping Control
Refer to 2 Operating Modes and On-Chip Memory.
PSELx
Interrupt Source Promoted
43210
0
0
0
X
X
Reserved (Default to IRQ)
00100
Reserved (Default to IRQ)
00101
Reserved (Default to IRQ)
00110
IRQ
00111
Real-Time Interrupt
01000
Timer Input Capture 1
01001
Timer Input Capture 2
01010
Timer Input Capture 3
01011
Timer Output Compare 1
01100
Timer Output Compare 2
01101
Timer Output Compare 3
01110
Timer Output Compare 4
01111
Timer Input Capture 4/Output Compare 5
10000
Timer Overflow
10001
Pulse Accumulator Overflow
10010
Pulse Accumulator Input Edge
10011
SPI Serial Transfer Complete
10100
SCI Serial System
10101
Reserved (Default to IRQ)
10110
Reserved (Default to IRQ)
10111
Reserved (Default to IRQ)
1
1
X
X
X
Reserved (Default to IRQ)
CONFIG — COP, ROM Mapping, EEPROM Enables
$003F
Bit 7
654321
Bit 0
ROMAD
—
CLKX
PAREN
NOSEC
NOCOP
ROMON
EEON
RESET:
—
1
—
————
—



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