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M68HC11KA Datasheet(PDF) 33 Page - Motorola, Inc |
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M68HC11KA Datasheet(HTML) 33 Page - Motorola, Inc |
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33 / 68 page ![]() MC68HC11KA4 MOTOROLA MC68HC11KA4TS/D 33 DDA[7:0] —Data Direction for Port A 0 = Bits set to zero to configure corresponding I/O pin for input only 1 = Bits set to one to configure corresponding I/O pin for output Reset state is mode dependent. In single-chip or bootstrap modes, port B pins are high impedance in- puts with selectable internal pull-up resistors. In expanded or test modes, port B pins are high order ad- dress outputs and PORTB is not in the memory map. DDB[7:0] — Data Direction for Port B 0 = Bits set to zero to configure corresponding I/O pin for input only 1 = Bits set to one to configure corresponding I/O pin for output Reset state is mode dependent. In single-chip or bootstrap modes, port F pins are high-impedance in- puts with selectable internal pull-up resistors. In expanded or test modes, port F pins are low order ad- dress outputs and PORTF is not in the memory map. DDRA — Data Direction Register for Port A $0001 Bit 7 654321 Bit 0 DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 RESET: 0000000 0 PORTB —Port B Data $0004 Bit 7 654321 Bit 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 S. Chip or Boot: PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 RESET: UUUUUUU U Expan. or Test: ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 DDRB — Data Direction Register for Port B $0002 Bit 7 654321 Bit 0 DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 RESET: 0000000 0 PORTF — Port F Data $0005 Bit 7 654321 Bit 0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 S. Chip or Boot: PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 RESET: UUUUUUU U Expan. or Test: ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 |
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