AD9643 datasheet(13/36 Pages) AD

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AD9643

Rev. A | Page 13 of 36

Pin No.

Mnemonic

Type

Description

D4−

Output

Channel A/Channel B LVDS Output Data 4—Complement.

D5+

Output

Channel A/Channel B LVDS Output Data 5—True.

D5−

Output

Channel A/Channel B LVDS Output Data 5—Complement.

D6+

Output

Channel A/Channel B LVDS Output Data 6—True.

D6−

Output

Channel A/Channel B LVDS Output Data 6—Complement.

D7+

Output

Channel A/Channel B LVDS Output Data 7—True.

D7−

Output

Channel A/Channel B LVDS Output Data 7—Complement.

D8+

Output

Channel A/Channel B LVDS Output Data 8—True.

D8−

Output

Channel A/Channel B LVDS Output Data 8—Complement.

D9+

Output

Channel A/Channel B LVDS Output Data 9—True.

D9−

Output

Channel A/Channel B LVDS Output Data 9—Complement.

D10+

Output

Channel A/Channel B LVDS Output Data 10—True.

D10−

Output

Channel A/Channel B LVDS Output Data 10—Complement.

D11+

Output

Channel A/Channel B LVDS Output Data 11—True.

D11−

Output

Channel A/Channel B LVDS Output Data 11—Complement.

D12+

Output

Channel A/Channel B LVDS Output Data 12—True.

D12−

Output

Channel A/Channel B LVDS Output Data 12—Complement.

D13+ (MSB)

Output

Channel A/Channel B LVDS Output Data 13—True.

D13− (MSB)

Output

Channel A/Channel B LVDS Output Data 13—Complement.

OR+

Output

Channel A/Channel B LVDS Overrange—True.

OR−

Output

Channel A/Channel B LVDS Overrange—Complement.

DCO+

Output

Channel A/Channel B LVDS Data Clock Output—True.

DCO−

Output

Channel A/Channel B LVDS Data Clock Output—Complement.

SPI Control

SCLK

Input

SPI Serial Clock.

SDIO

Input/Output

SPI Serial Data I/O.

CSB

Input

SPI Chip Select (Active Low).

Output Enable and Power-Down

OEB

Input/Output

Output Enable Input (Active Low).

PDWN

Input/Output

Power-Down Input (Active High). The operation of this pin

depends on the SPI mode and can be configured as power-down

or standby (see Table 14).

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