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AD9643 Datasheet(PDF) 14 Page - Analog Devices |
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AD9643 Datasheet(HTML) 14 Page - Analog Devices |
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14 / 36 page ![]() AD9643 Rev. A | Page 14 of 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK+ CLK– SYNC DNC DNC DNC DNC (LSB) B D0–/D1– (LSB) B D0+/D1+ DRVDD B D2–/D3– B D2+/D3+ B D4–/D5– B D4+/D5+ B D6–/D7– B D6+/D7+ NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. PDWN OEB CSB SCLK SDIO OR+ OR– A D12+/D13+ (MSB) A D12–/D13– (MSB) A D10+/D11+ A D10–/D11– DRVDD A D8+/D9+ A D8–/D9– A D6+/D7+ A D6–/D7– 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AD9643 CHANNEL MULTIPLEXED (EVEN/ODD) LVDS TOP VIEW (Not to Scale) PIN 1 INDICATOR Figure 5. LFCSP Channel Multiplexed (Even/Odd) LVDS Pin Configuration (Top View) Table 9. Pin Function Descriptions for Channel Multiplexed (Even/Odd) LVDS Mode Pin No. Mnemonic Type Description ADC Power Supplies 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 49, 50, 53, 54, 59, 60, 63, 64 AVDD Supply Analog Power Supply (1.8 V Nominal). 4, 5, 6, 7 DNC Do Not Connect. Do not connect to this pin. 0 AGND, Exposed Paddle Ground Analog Ground. The exposed thermal paddle on the bottom of the package provides the analog ground for the part. This exposed paddle must be connected to ground for proper operation. ADC Analog 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 55 DNC Do Not Connect. Do not connect to this pin. 56 DNC Do Not Connect. Do not connect to this pin. 58 DNC Do Not Connect. Do not connect to this pin. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. This pin should be decoupled to ground using a 0.1 μF capacitor. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. Digital Input 3 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 8 B D0−/D1− (LSB) Output Channel B LVDS Output Data 0/Data 1—Complement. 9 B D0+/D1+ (LSB) Output Channel B LVDS Output Data 0/Data 1—True. 11 B D2−/D3− Output Channel B LVDS Output Data 2/Data 3—Complement. 12 B D2+/D3+ Output Channel B LVDS Output Data 2/Data 3—True. 13 B D4−/D5− Output Channel B LVDS Output Data 4/Data 5—Complement. |
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