ADG5213 datasheet(17/20 Pages) AD

Part #	ADG5213

Description	High Voltage Latch-Up Proof, Quad SPST Switches 0.07 pC charge injection

PDF	20 Pages

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Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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17 / 20 page

ADG5212/ADG5213

Rev. 0 | Page 17 of 20

TRENCH ISOLATION

In the ADG5212 and ADG5213, an insulating oxide layer

(trench) is placed between the NMOS and the PMOS transistors

of each CMOS switch. Parasitic junctions, which occur between

the transistors in junction isolated switches, are eliminated, and

the result is a completely latch-up proof switch.

In junction isolation, the N and P wells of the PMOS and NMOS

transistors form a diode that is reverse-biased under normal

operation. However, during overvoltage conditions, this diode

can become forward-biased. A silicon controlled rectifier (SCR)

type circuit is formed by the two transistors, causing a significant

amplification of the current that, in turn, leads to latch-up. With

trench isolation, this diode is removed and the result is a latch-

up proof switch.

NMOS

PMOS

PWELL

N WELL

BURIED OXIDE LAYER

HANDLE WAFER

TRENCH

Figure 32. Trench Isolation

ADG5213 Datasheet(PDF) 17 Page - Analog Devices