TMP006

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SBOS518

– MAY 2011

TIMING DIAGRAMS

The TMP006 is two-wire and SMBus-compatible. Figure 7 and Figure 8 illustrate the timing for the various

operations on the TMP006. Parameters for Figure 7 are defined in Table 11. Bus definitions are given below.

Table 11. Timing Diagram Definitions

FAST MODE

HIGH-SPEED MODE

PARAMETER

TEST CONDITIONS

MIN

MAX

MIN

MAX

UNIT

0.001

0.4

0.001

3.4

MHz

0.001

0.4

0.001

2.75

MHz

Bus free time between STOP and START

600

160

ns

condition

Hold time after repeated START condition.

After this period, the first clock is

100

100

ns

generated.

Repeated START condition setup time

100

100

ns

STOP condition setup time

100

100

ns

Data hold time

ns

Data setup time

100

10

ns

1300

160

ns

1300

200

ns

SCL clock high period

600

60

ns

Clock/data fall time

300

ns

Clock/data rise time

300

160

ns

Clock/data rise time for SCLK

≤ 100 kHz

1000

ns

(1)

For cases with fall time of SCL less than 20 ns and/or the rise or fall time of SDA less than 20 ns, the hold time should be greater than

20 ns.

(2)

For cases with a fall time of SCL less than 10 ns and/or the rise or fall time of SDA less than 10 ns, the hold time should be greater than

10 ns.

Bus Idle: Both SDA and SCL lines remain high.

Start Data Transfer: A change in the state of the SDA line from high to low while the SCL line is high defines a

START condition. Each data transfer is initiated with a START condition.

Stop Data Transfer: A change in the state of the SDA line from low to high while the SCL line is high defines a

STOP condition. Each data transfer terminates with a STOP or a repeated START condition.

Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and

is determined by the master device. The receiver acknowledges the transfer of data.

Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device

that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA

line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken into

account. On a master receive, data transfer termination can be signaled by the master generating a

Not-Acknowledge on the last byte that has been transmitted by the slave.

In order for the two-wire bus to operate at frequencies above 400 kHz, the master device must issue a

High-speed mode (Hs-mode) master code (0000100X) as the first byte after a START condition to switch the bus

to high-speed operation. The TMP006 does not acknowledge this byte, but switches the input filters on SDA and

SCL and the output filter on SDA to operate in Hs-mode, allowing transfers at up to 3.4 MHz. After the Hs-mode

master code has been issued, the master transmits a two-wire slave address to initiate a data transfer operation.

The bus continues to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving the STOP

condition, the TMP006 switches the input and output filter back to fast-mode operation.

Copyright

© 2011, Texas Instruments Incorporated

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