1

StartBy

Master

ACKBy

TMP006

ACKBy

TMP006

ACKBy

TMP006

StopBy

Master

1

9

1

1

D7

D6

D5

D4

D3

D2

D1

D0

9

ACKBy

TMP006

1

D7

SDA

(Continued)

SCL

(Continued)

D6

D5

D4

D3

D2

D1

D0

9

9

SDA

SCL

0

0

0

0

0

0

(1)

P7

P6

P5

P4

P3

P2

P1

P0

¼

¼

Frame1Two-WireSlaveAddressByte

Frame2PointerRegisterByte

Frame4LSB

Frame3MSB

1

StartBy

Master

ACKBy

TMP006

ACKBy

TMP006

StartBy

Master

ACKBy

TMP006

ACKBy

Master

From

TMP006

1

9

1

9

1

9

1

9

SDA

SCL

0

0

0

R/

W

P7

P6

P5

P4

P3

P2

P1

P0

SDA

SCL

(Continued)

SDA

SCL

1

0

0

0

0

0

0

(1)

0

0

0

(1)

R/

W

D7

D6

D5

D4

D3

D2

D1

D0

StopBy

Master

NACKBy

Master

(2)

From

TMP006

1

9

D7

D6

D5

D4

D3

D2

D1

D0

Frame1Two-WireSlaveAddressByte

Frame2PointerRegisterByte

Frame3Two-WireSlaveAddressByte

Frame4MSB

Frame5LSB

TMP006

SBOS518

– MAY 2011

www.ti.com

(1) Slave address 1000000 shown. Slave address changes for the TMP006 depend on the ADR1 and ADR0 pin connection. See Package

Information for more details.

Figure 7. Two-Wire Timing Diagram for Write Word Format

(1) Slave address 1000000 shown.

(2) Master must leave SDA high to terminate a two-byte read operation.

Figure 8. Two-Wire Timing Diagram for Two-Byte Read Format

14

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