ISL62391IRTZ datasheet(18/20 Pages) INTERSIL

18 / 20 page

FN6666.5

April 7, 2011

Where:

-IVALLEY is the difference of the DC component of the

inductor current minus 1/2 of the inductor ripple current

-IPEAK is the sum of the DC component of the inductor

current plus 1/2 of the inductor ripple current

-tON is the time required to drive the device into

saturation

-tOFF is the time required to drive the device into cut-off

Selecting The Bootstrap Capacitor

The selection of the bootstrap capacitor is written as

Equation 26:

Where:

-Qg is the total gate charge required to turn on the

high-side MOSFET

ΔVBOOT, is the maximum allowed voltage decay across

the boot capacitor each time the high-side MOSFET is

switched on

As an example, suppose the high-side MOSFET has a total

gate charge Qg, of 25nC at VGS = 5V, and a ΔVBOOT of

200mV. The calculated bootstrap capacitance is 0.125µF; for

a comfortable margin, select a capacitor that is double the

calculated capacitance. In this example, 0.22µF will suffice.

Use an X7R or X5R ceramic capacitor.

Layout Considerations

As a general rule, power should be on the bottom layer of

the PCB and weak analog or logic signals are on the top

layer of the PCB. The ground-plane layer should be adjacent

to the top layer to provide shielding. The ground plane layer

should have an island located under the IC, the

compensation components, and the FSET components. The

island should be connected to the rest of the ground plane

layer at one point.

Because there are two SMPS outputs and only one PGND

pin, the power train of both channels should be laid out

symmetrically. The line of bilateral symmetry should be

drawn through pins 4 and 18. This layout approach ensures

that the controller does not favor one channel over another

during critical switching decisions. Figure 29 illustrates one

example of how to achieve proper bilateral symmetry.

Signal Ground and Power Ground

The bottom of the ISL62391, ISL62392, ISL62391C and

ISL62392C TQFN package is the signal ground (GND)

terminal for analog and logic signals of the IC. Connect the

GND pad of the ISL62391, ISL62392, ISL62391C and

ISL62392C to the island of ground plane under the top layer

using several vias for a robust thermal and electrical

conduction path. Connect the input capacitors, the output

capacitors, and the source of the lower MOSFETs to the

power ground plane.

PGND (Pin 19)

This is the return path for the pull-down of the LGATE

low-side MOSFET gate driver. Ideally, PGND should be

connected to the source of the low-side MOSFET with a

low-resistance, low-inductance path.

VIN (Pin 17)

The VIN pin should be connected close to the drain of the

high-side MOSFET, using a low resistance and low

inductance path.

VCC (Pin 4)

For best performance, place the decoupling capacitor very

close to the VCC and GND pins.

PVCC (Pin 18)

For best performance, place the decoupling capacitor very

close to the PVCC and respective PGND pin, preferably on

the same side of the PCB as the ISL62391, ISL62392,

ISL62391C and ISL62392C ICs.

EN (Pins 11 and 24), and PGOOD (Pin 1)

These are logic signals that are referenced to the GND pin.

Treat as a typical logic signal.

OCSET (Pins 10 and 25) and ISEN (Pins 9 and 26)

For DCR current sensing, the current-sense network,

consisting of ROCSET and CSEN, needs to be connected to

the inductor pads for accurate measurement. Connect

BOOT

ΔV

BOOT

------------------------

(EQ. 26)

INDUCTOR

VIAS TO

GROUND

PLANE

VIN

VOUT

PHASE

NODE

GND

OUTPUT

CAPACITORS

LOW-SIDE

MOSFETS

INPUT

CAPACITORS

SCHOTTKY

DIODE

HIGH-SIDE

MOSFETS

FIGURE 29. TYPICAL POWER COMPONENT PLACEMENT

OUTPUT

CAPACITORS

SCHOTTKY

DIODE

LOW-SIDE

MOSFETS

INPUT

CAPACITORS

INDUCTOR

HIGH-SIDE

MOSFETS

GND

VIN

VIAS TO

GROUND

PLANE

PHASE

NODE

LINEOFSYMMETRY

PIN4 (VCC)

PIN18 (PVCC)

ISL6239

PGNDPLANE

PHASEPLANES

VOUTPLANES

VINPLANE

FIGURE 30. SYMMETRIC LAYOUT GUIDE

ISL62391, ISL62392, ISL62391C, ISL62392C

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