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ISL62391IRTZ Datasheet(PDF) 19 Page - Intersil Corporation |
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ISL62391IRTZ Datasheet(HTML) 19 Page - Intersil Corporation |
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19 / 20 page ![]() 19 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6666.5 April 7, 2011 ROCSET to the phase-node side pad of the inductor, and connect CSEN to the output side pad of the inductor. The ISEN resistor should also be connected to the output pad of the inductor with a separate trace. Connect the OCSET pin to the common node of node of ROCSET and CSEN. For resistive current sensing, connect ROCSET from the OCSET pin to the inductor side of the resistor pad. The ISEN resistor should be connected to the VOUT side of the resistor pad. In both current-sense configurations, the resistor and capacitor sensing elements, with the exclusion of the current sense power resistor, should be placed near the corresponding IC pin. The trace connections to the inductor or sensing resistor should be treated as Kelvin connections. FB (Pins 7 and 28), and VOUT (Pins 8 and 27) The VOUT pin is used to generate the R3 synthetic ramp voltage and for soft-discharge of the output voltage during shutdown events. This signal should be routed as close to the regulation point as possible. The input impedance of the FB pin is high, so place the voltage programming and loop compensation components close to the VOUT, FB, and GND pins, keeping the high impedance trace short. FSET (Pins 2 and 6) This pin requires a quiet environment. The resistor RFSET and capacitor CFSET should be placed directly adjacent to this pin. Keep fast moving nodes away from this pin. LGATE (Pins 15 and 20) The signal going through this trace is both high dv/dt and high di/dt, with high peak charging and discharging current. Route this trace in parallel with the trace from the PGND pin. These two traces should be short, wide, and away from other traces. There should be no other weak signal traces in proximity with these traces on any layer. BOOT (Pins 14 and 21), UGATE (Pins 13 and 22), and PHASE (Pins 12 and 23) The signals going through these traces are both high dv/dt and high di/dt, with high peak charging and discharging current. Route the UGATE and PHASE pins in parallel with short and wide traces. There should be no other weak signal traces in proximity with these traces on any layer. Copper Size for the Phase Node The parasitic capacitance and parasitic inductance of the phase node should be kept very low to minimize ringing. It is best to limit the size of the PHASE node copper in strict accordance with the current and thermal management of the application. An MLCC should be connected directly across the drain of the upper MOSFET and the source of the lower MOSFET to suppress the turn-off voltage spike. ISL62391, ISL62392, ISL62391C, ISL62392C |
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