LH28F008SC datasheet(18/38 Pages) SHARP

18 / 38 page

LH28F008SC

8M (1M × 8) Flash Memory

Figure 10. Set Block and Master Lock-Bit Flowchart

START

BUS

OPERATION

COMMAND

COMMENTS

WRITE 60H

BLOCK/DEVICE ADDRESS

SR.7 =

FULL STATUS

CHECK IF DESIRED

SET LOCK-BIT

COMPLETED

WRITE 01H/F1H

BLOCK/DEVICE ADDRESS

SET LOCK-BIT

SUCCESSFUL

VPP RANGE

ERROR

READ STATUS

(see above)

SR.3 =

Write

Read

Standby

Set

Block/Master

Lock-Bit Setup

Set

Block or Master

Lock-Bit Confirm

Data = 60H

Addr = Block Address (Block),

Device Address (Master)

Status Register Data

Check SR.7

1 = WSM Ready

0 = WSM Busy

Data = 01H (Block)

F1H (Master)

Addr = Block Address (Block),

Device Address (Master)

Repeat for subsequent lock-bit set operations.

Full status check can be done after each lock-bit set operation

or after a sequence of lock-bit set operations.

Write FFH after the last lock-bit set operation to place device

in read array mode.

BUS

OPERATION

COMMAND

FULL STATUS CHECK PROCEDURE

COMMENTS

Standby

Check SR.3

1 = VPP Error Detect

Check SR.1

1 = Device Protect Detect

RP = VIH

(Set Master Lock-Bit Operation)

RP = VIH, Master Lock-Bit is Set

(Set Block Lock-Bit Operation)

Check SR.4, 5

Both 1 = Command

Sequence Error

Check SR.4

1 = Set Lock-Bit Error

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status

before full status is checked.

If error is detected clear the Status Register before attempting

retry or other error recovery.

28F008SC-10

READ STATUS REGISTER

SR.1 =

SR.4, 5 =

SR.4 =

COMMAND

SEQUENCE

ERROR

DEVICE

PROTECT

ERROR

SET LOCK-BIT

ERROR

LH28F008SC Datasheet(PDF) 18 Page - Sharp Corporation

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