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STM32F407IG Datasheet(PDF) 117 Page - STMicroelectronics |
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STM32F407IG Datasheet(HTML) 117 Page - STMicroelectronics |
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117 / 154 page ![]() STM32F405xx, STM32F407xx Electrical characteristics Doc ID 022152 Rev 1 117/154 Figure 47. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. th(BL_NOE) FSMC_BL hold time after FSMC_NOE high TBD - ns tsu(Data_NE) Data to FSMC_NEx high setup time TBD - ns tsu(Data_NOE) Data to FSMC_NOEx high setup time TBD - ns th(Data_NOE) Data hold time after FSMC_NOE high TBD - ns th(Data_NE) Data hold time after FSMC_NEx high TBD - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - TBD ns tw(NADV) FSMC_NADV low time - TBD ns 1. CL = 15 pF. 2. Preliminary values. 3. TBD stands for “to be defined”. Table 71. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2)(3) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time TBD TBD ns tv(NWE_NE) FSMC_NEx low to FSMC_NWE low TBD TBD ns tw(NWE) FSMC_NWE low time TBD TBD ns th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time TBD - ns Table 70. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2)(3) Symbol Parameter Min Max Unit NBL Data FSMC_NEx FSMC_NBL[1:0] FSMC_D[15:0] tv(BL_NE) th(Data_NWE) FSMC_NOE Address FSMC_A[25:0] tv(A_NE) tw(NWE) FSMC_NWE tv(NWE_NE) t h(NE_NWE) th(A_NWE) th(BL_NWE) tv(Data_NE) tw(NE) ai14990 FSMC_NADV(1) t v(NADV_NE) tw(NADV) |
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