GS9060 datasheet(9/61 Pages) GENNUM

9 / 61 page

GS9060 Data Sheet

22208 - 8

January 2007

9 of 61

SDOUT_TDO

Synchronous

with

SCLK_TCK

Output

CONTROL SIGNAL OUTPUT

Signal levels are LVCMOS/LVTTL compatible.

Serial Data Output / Test Data Output

Host Mode (JTAG/HOST = LOW)

SDOUT_TDO operates as the host interface serial output,

SDOUT, used to read status and configuration information from

the internal registers of the device.

JTAG Test Mode (JTAG/HOST = HIGH)

SDOUT_TDO operates as the JTAG test data output, TDO.

SDIN_TDI

Synchronous

with

SCLK_TCK

Input

CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Serial Data In / Test Data Input

Host Mode (JTAG/HOST = LOW)

SDIN_TDI operates as the host interface serial input, SDIN, used

to write address and configuration information to the internal

registers of the device.

JTAG Test Mode (JTAG/HOST = HIGH)

SDIN_TDI operates as the JTAG test data input, TDI.

NOTE: If the host interface is not being used, tie this pin HIGH.

SCLK_TCK

Non

Synchronous

Input

CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Serial Data Clock / Test Clock.

Host Mode (JTAG/HOST = LOW)

SCLK_TCK operates as the host interface burst clock, SCLK.

Command and data read/write words are clocked into the device

synchronously with this clock.

JTAG Test Mode (JTAG/HOST = HIGH)

SCLK_TCK operates as the JTAG test clock, TCK.

NOTE: If the host interface is not being used, tie this pin HIGH.

DATA_ERROR

Synchronous

with PCLK

Output

STATUS SIGNAL OUTPUT

Signal levels are LVCMOS/LVTTL compatible.

The DATA_ERROR signal will be LOW when an error within the

received data stream has been detected by the device. This pin

is a logical 'OR'ing of all detectable errors listed in the internal

ERROR_STATUS register.

Once an error is detected, DATA_ERROR will remain LOW until

the start of the next video frame / field, or until the

ERROR_STATUS register is read via the host interface.

The DATA_ERROR signal will be HIGH when the received data

stream has been detected without error.

NOTE: It is possible to program which error conditions are

monitored by the device by setting appropriate bits of the

ERROR_MASK register HIGH. All error conditions are detected

by default.

FIFO_LD

Synchronous

with PCLK

Output

CONTROL SIGNAL OUTPUT

Signal levels are LVCMOS/LVTTL compatible.

Used as a control signal for external FIFO(s).

Normally HIGH but will go LOW for one PCLK period at SAV.

Table 1-1: Pin Descriptions (Continued)

Number

Name

Timing

Type

Description

GS9060 Datasheet(PDF) 9 Page - Gennum Corporation

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