GS9060 datasheet(29/61 Pages) GENNUM

29 / 61 page

GS9060 Data Sheet

22208 - 8

January 2007

29 of 61

If after four attempts lock has not been achieved, the lock detection algorithm will

enter into PLL lock mode. In this mode, the reclocker will attempt to lock to the input

data stream without detecting SMPTE TRS or DVB-ASI sync words. This

unassisted process can take up to 10ms to achieve lock.

When reclocker lock as indicated by the internal pll_lock signal is achieved in this

mode, data will be passed directly to the parallel outputs without any further

processing taking place and the LOCKED signal will be asserted HIGH if and only

if the SMPTE_BYPASS and DVB_ASI input pins are set LOW.

3.6.1 Input Control Signals

The GS9060 contains three input control signals which determine how the device

locks to the input.

It is required that the application layer set the SMPTE_BYPASS and DVB_ASI

inputs to reflect the appropriate input data format. If either is configured incorrectly,

the device will not lock to the input data stream, and the DATA_ERROR pin will be

set LOW.

The third input signal, RC_BYP, allows the application layer to determine whether

the serial digital loop-through output will be a reclocked or buffered version of the

input, Section 3.4.2 on page 27. Table 3-2 shows the required settings for various

input formats.

Table 3-2: Input Control Signals

Format

Pin Settings

SMPTE_BYPASS

DVB_ASI

SD SMPTE

HIGH

LOW

DVB-ASI

LOW

HIGH

NOT SMPTE OR DVB-ASI*

LOW

*NOTE: See Section 3.9 on page 36 for a complete description of Data-Through mode.

GS9060 Datasheet(PDF) 29 Page - Gennum Corporation