VSP5621 datasheet(9/41 Pages) TI1

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VSP5620

VSP5621

VSP5622

www.ti.com

SBES022

– JULY 2011

ELECTRICAL CHARACTERISTICS: VSP5622

All specifications at TA = +25°C, supply voltage = +3.3 V, conversion rate = 17.5 MHz, and four-channel mode, unless

otherwise noted.

VSP5622

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUT

Allowable input voltage

VDD

Full-scale range

Gain = 1 V/V

VPP

Input capacitor

DIGITAL INPUT

Positive-going threshold

VT+

DVDD_IO

× 0.7

Negative-going threshold

VT–

DVDD_IO

× 0.3

Hysteresis (VT+ – VT–)

ΔVT

DVDD_IO

× 0.13

Input current

IIN

±1

µA

Input capacitor

DIGITAL OUTPUT

IOH = –2 mA

DVDD_IO

– 0.45

High-level output voltage

VOH

IOH = –4 mA

DVDD_IO

– 0.50

IOH = –8 mA

DVDD_IO

– 0.50

IOL = 2 mA

0.35

Low-level output voltage

VOL

IOL = 4 mA

0.50

IOL = 8 mA

0.65

CMOS data output bit rate

MHz

LVDS DRIVER (TA, TB, TCLK)

Differential steady-state output

|VOD|

RL = 100 Ω

300

350

400

voltage adjustment range

Differential steady-state output

|VOD|

Steps

adjustment step

Differential steady-state output

|VOD|

–30

voltage tolerance

Change in the steady-state

differential output voltage magnitude

Δ|VOD|

between opposite binary states

Steady-state common-mode output

VOC(SS)

RL = 100 Ω

1.125

1.375

voltage

Peak-to-peak common-mode output

VOC(PP)

150

voltage

Short-circuit output current

IOS

VO = 0 V (VO = TA, TB, TCLK)

–6

±24

VO = 0 V to LVDD

Hi-Z output current

IOZ

±10

µA

(VO = TA, TB, TCLK)

Transition time, differential output

tLR/tLF

0.75

1.5

voltage

TCLK clock rate

MHz

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