LPC4350 datasheet(107/149 Pages) PHILIPS

107 / 149 page

LPC4350_30_20_10

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Objective data sheet

Rev. 3.1 — 5 January 2012

107 of 149

NXP Semiconductors

LPC4350/30/20/10

32-bit ARM Cortex-M4/M0 microcontroller

11.6 I2S-bus interface

[1]

Clock to the I2S-bus interface BASE_APB1_CLK = 150 MHz; peripheral clock to the I2S-bus interface

PCLK = BASE_APB1_CLK / 12. I2S clock cycle time Tcy(clk) = 79.2 ns; corresponds to the SCK signal in the

I2S-bus specification.

Table 15.

Dynamic characteristics: I2S-bus interface pins

Tamb =25 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF. Conditions and data

refer to I2S0 and I2S1 pins. Simulated values.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

common to input and output

rise time

fall time

tWH

pulse width HIGH

on pins I2Sx_TX_SCK

and I2Sx_RX_SCK

<tbd>

tWL

pulse width LOW

on pins I2Sx_TX_SCK

and I2Sx_RX_SCK

<tbd>

output

tv(Q)

data output valid time on pin I2Sx_TX_SDA

[1]

-4.4

on pin I2Sx_TX_WS

4.3

input

tsu(D)

data input set-up time on pin I2Sx_RX_SDA

[1]

-0

on pin I2Sx_RX_WS

0.20

th(D)

data input hold time

on pin I2Sx_RX_SDA

[1]

-3.7

on pin I2Sx_RX_WS

3.9

Fig 25. I2S-bus timing (transmit)

002aag497

I2Sx_TX_SCK

I2Sx_TX_SDA

I2Sx_TX_WS

Tcy(clk)

tWH

tWL

tv(Q)

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