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Data Sheet

AD5116

Rev. 0 | Page 15 of 16

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates a voltage divider at

wiper-to-B and wiper-to-A that is proportional to the input

voltage at A to B, as shown in Figure 43. Unlike the polarity of

VDD to GND, which must be positive, voltage across A-to-B, W-

to-A, and W-to-B can be at either polarity.

VIN

VOUT

Figure 43. Potentiometer Mode Configuration

If ignoring the effect of the wiper resistance for simplicity,

connecting Terminal A to 5 V and Terminal B to ground

produces an output voltage at the Wiper W to Terminal B

ranging from 0 V to 5 V. The general equation defining the

output voltage at VW, with respect to ground for any valid

input voltage applied to Terminal A and Terminal B, is:









)

(

)

(

)

(

(6)

where:

RWB(D)

can be obtained from Equation 1 or Equation 2.

RAW(D)

can be obtained from Equation 3 to Equation 5 .

Operation of the digital potentiometer in the divider mode

results in a more accurate operation over temperature. Unlike

the rheostat mode, the output voltage is dependent mainly

on the ratio of the internal resistors, RWA and RWB, and not the

absolute values. Therefore, the temperature drift reduces to

5 ppm/°C.

TERMINAL VOLTAGE OPERATING RANGE

The AD5116 is designed with internal ESD diodes for

protection. These diodes also set the voltage boundary of

the terminal operating voltages. Positive signals present on

Terminal A, Terminal B, or Terminal W that exceed VDD are

clamped by the forward-biased diode. There is no polarity

constraint between VA, VW, and VB, but they cannot be higher

than VDD or lower than GND.

POWER-UP SEQUENCE

Because of the ESD protection diodes that limit the voltage

compliance at Terminal A, Terminal B, and Terminal W (see

Figure 44), it is important to power on VDD before applying

any voltage to Terminal A, Terminal B, and Terminal W.

Otherwise, the diodes are forward-biased such that VDD is

powered on unintentionally and can affect other parts of the

circuit. Similarly, VDD should be powered down last. The ideal

power-on sequence is in the following order: GND, VDD, and

VA/VB/VW. The order of powering VA, VB, and VW is not

important as long as they are powered on after VDD. The

states of the PU and PD pins can be logic low or floating,

but they should not be logic high during power-on.

GND

VDD

Figure 44. Maximum Terminal Voltages Set by VDD and VSS

LAYOUT AND POWER SUPPLY BIASING

It is always a good practice to use compact, minimum lead

length layout design. The leads to the input should be as direct

as possible with a minimum conductor length. Ground paths

should have low resistance and low inductance. It is also good

practice to bypass the power supplies with quality capacitors.

Low equivalent series resistance (ESR) 1 μF to 10 μF tantalum

or electrolytic capacitors should be applied at the supplies to

minimize any transient disturbance and to filter low frequency

ripple. Figure 45 illustrates the basic supply bypassing config-

uration for the AD5116.

AD5116

10µF

0.1µF

VDD

AGND

GND

Figure 45. Power Supply Bypassing

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