ADM1075 datasheet(22/52 Pages) AD

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ADM1075

Data Sheet

Rev. A | Page 22 of 52

FLB

ISET

0.1V

CURRENT LIMIT

REFERENCE

Figure 47. Interaction of Soft Start, Foldback, and ISET Current Limits

SETTING THE CURRENT LIMIT (ISET)

The maximum current limit is partially determined by selecting

a sense resistor to match the current sense voltage limit on the

controller for the desired load current. However, as currents

become larger, the sense resistor value becomes smaller and

resolution can be difficult to achieve when selecting the appropri-

ate sense resistor value. The ADM1075 provides an adjustable

sense voltage limit to deal with this issue. The device allows the

user to program the required current sense voltage limit from

15 mV to 25 mV for the ADM1075-1 and from 30 mV to 50 mV

for the ADM1075-2.

The default value of 20 mV/40 mV is achieved by connecting

the ISET pin directly to the VCAP pin (VCAP > 1.65 V ISET

reference select threshold). This configures the device to use an

internal 1 V reference, which equates to 20 mV/40 mV at the

sense inputs (see Figure 48(a)).

ADM1075

(PARTIAL)

VCAP

ISET

VEE

(A)

(B)

VCAP

ISET

ADM1075

(PARTIAL)

Figure 48. (a) Fixed 20 mV/40 mV Current Sense Limit

(b) Adjustable 15 mV to 50 mV Current Sense Limit

To set the sense voltage in the 15 mV to 50 mV range, a resistor

divider is used to apply a reference voltage to the ISET pin (see

Figure 48(b)). The VCAP pin has a 2.7 V internally generated

voltage that can be used to set a voltage at the ISET pin.

Assuming VISET equals the voltage on the ISET pin, the resistor

divider should be sized to set the ISET voltage as follows:

VISET = (VSENSE × 50) for ADM1075-1 or

VISET = (VSENSE × 25) for ADM1075-2

where VSENSE is the sense voltage limit. The VCAP rail can also

be used as the pull-up supply for setting the I2C address. The

VCAP pin should not be used for any other purpose. To

guarantee accuracy specifications, care must be taken to not

load the VCAP pin by more than 100 μA.

SOFT START

A capacitor connected to the SS pin determines the inrush

current profile. Before the FET is enabled, the output voltage of

the current limit reference selector block is clamped at 100 mV.

This, in turn, holds the current limit reference at approximately

2 mV for the ADM1075-1 or 4 mV for the ADM1075-2. When

the FET is requested to turn on, the SS pin is held at ground

until the voltage between the SENSE+ and SENSE− pins

(VSENSE) reaches the circuit breaker voltage, VCB.

VCB = VSENSECL − VCBOS

When the load current generates a sense voltage equal to VCB, a

10 μA current source is enabled, which charges the SS capacitor

and results in a linear ramping voltage on the SS pin. The

current limit reference also ramps up accordingly, allowing the

regulated load current to ramp up, while avoiding sudden

transients during power-up. The SS capacitor value is given by

ISET

where

ISS = 10 μA, and t is the SS ramp time.

For example, a 10 nF capacitor gives a soft start time of 1 ms.

Note that the SS voltage may intersect with the PLIM or

foldback (FLB) voltage, and the current limit reference may

change to follow PLIM (see Figure 47). This has minimal

impact on startup because the output voltage rises at a similar

rate to SS.

CONSTANT POWER FOLDBACK (PLIM)

Foldback is a method that actively reduces the current limit as

the voltage drop across the FET increases. It keeps the power

across the FET below the programmed value during power-up,

overcurrent, or short-circuit events. This allows a smaller FET

to be used, resulting in significant cost savings. The foldback

method employed is a constant power foldback scheme, meaning

power in the FET is held constant regardless of the VDS of the

FET. This simplifies the task of ensuring that the FET is always

operating within the SOA region.

The ADM1075 detects the voltage drop across the FET by

monitoring the voltage on the drain of the FET (via the PLIM

pin). The device relies on the principle that the source of the

FET is at the most negative expected supply voltage, and the

magnitude of the drain voltage is relative to that of the VDS of

the FET. Using a resistor divider from the drain of the FET to

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