ADM1075 datasheet(24/52 Pages) AD

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ADM1075

Data Sheet

Rev. A | Page 24 of 52

timing cycle. The TIMER pin is pulled up with 3 μA. When the

TIMER reaches the VTIMERH threshold (1.0 V), the first portion

of the initial cycle is complete. The 100 μA current source then

pulls down the TIMER pin until it reaches VTIMERL (0.05 V). The

initial cycle duration is related to CTIMER by the following

equation:

μA

100

)

(

μA

TIMER

TIMERL

TIMERH

TIMER

TIMERH

INITIAL

−

For example, a 470 nF capacitor results in a power-up delay of

approximately 160 ms. Provided the UV and OV detectors are

inactive when the initial timing cycle terminates, the device is

ready to start a hot swap operation.

When the voltage across the sense resistor reaches the circuit

breaker trip voltage, VCB, the 60 μA timer pull-up current is

activated, and the gate begins to regulate the current at the current

limit. This initiates a ramp-up on the TIMER pin. If the sense

voltage falls below this circuit breaker trip voltage before the

TIMER pin reaches VTIMERH (1.0 V), the 60 μA pull-up is

disabled, and the 2 μA pull-down is enabled.

The circuit breaker trip voltage is not the same as the hot swap

sense voltage current limit. There is a small circuit breaker

offset, VCBOS, which means that the timer actually starts a short

time before the current reaches the defined current limit.

However, if the overcurrent condition is continuous and the

sense voltage remains above the circuit breaker trip voltage, the

60 μA pull-up remains active and the FET remains in regulation.

This allows the TIMER pin to reach VTIMERH and initiate the

GATE shutdown. The LATCH pin is pulled low immediately.

In latch-off mode, the TIMER pin is switched to the 2 μA pull-

down when it reaches the VTIMERH threshold. The LATCH pin

remains low. While the TIMER pin is being pulled down, the

hot swap controller is kept off and cannot be turned back on.

When the voltage on the TIMER pin goes below the VTIMERL

threshold, the hot swap controller can be reenabled by toggling

the UVx pin or by using the PMBus OPERATION command to

toggle the ON bit from on to off and then on again.

HOT SWAP FAULT RETRY

The ADM1075 turns off the FET after an overcurrent fault.

With the default pin configuration, the part latches off after an

overcurrent fault and LATCH goes active low. This condition

can then be reset by either a power cycling event or a low signal

to either the SHDN input or RESTART input. It can also be

reset by toggling the UVx pin, using the PMBus operation

command or the PMBus power cycle command.

If the LATCH pin is connected to the SHDN pin, the part

makes seven attempts to hot swap before latching off. In this

mode, the part uses the TIMER pin to time a delay between

each attempt. In this way, a large load capacitance can be

charged using consecutive current limit periods.

The part can also be configured to autoretry an infinite number

of times with a 10 second cooling period between each retry.

Connecting LATCH to RESTART means that the part makes

one hot swap attempt between each cooling period. Connecting

LATCH to SHDN and GPO2/ALERT2 to RESTART means

that the part makes seven hot swap attempts between each

cooling period.

The duty cycle of the automatic retry cycle is set by the ratio of

2 μA/60 μA, which approximates to being on ~4% of the time.

The value of the timer capacitor determines the on time of this

cycle, which is calculated as follows:

tON = VTIMERH × (CTIMER/60 μA)

tOFF = (VTIMERH − VTIMERL) × (CTIMER/2 μA)

A 470 nF capacitor on the TIMER pin gives ~8 ms of on time

(for example, to meet 10 ms SOA), and ~220 ms off time.

FAST RESPONSE TO SEVERE OVERCURRENT

The ADM1075 features a very fast detection circuit that quickly

responds to severe overcurrent events such as short circuits.

Such an event may cause catastrophic damage if not controlled

very quickly. A fast response circuit ensures that the ADM1075

detects an overcurrent event at approximately 150% of the normal

current limit (ISET) and responds and controls the current

within 1 μs in most cases. The severe overcurrent threshold

and glitch filter times are digitally programmable through the

PMBus. The threshold can be selected as 125%, 150%, 200%, or

225% of the normal current limit, and the glitch filter time can

be set to 200 ns, 900 ns, 10.7 μs, or 57 μs. This sets a maximum

response time of 300 ns, 950 ns, 13 μs, or 60 μs.

UV AND OV

The ADM1075 monitors the supply voltage for undervoltage

(UV) and overvoltage (OV) conditions. The OV pin is con-

nected to the input of an internal voltage comparator, and its

voltage level is internally compared with a 1 V voltage reference.

The user can program the value of the OV hysteresis by varying

the top resistor of the resistor divider on the pin. This

impedance in combination with the 5 μA OV hysteresis current

(current turned on after OV trips) sets the OV hysteresis

voltage.

BOTTOM

TOP

THRESHOLD

RISING

)

μA

(

−

≈

TOP

RISING

FALLING

The UV detector is split into two separate pins, UVH and UVL.

The voltage on the UVH pin is compared internally to a 1 V

reference, whereas the UVL pin is compared to a 0.9 V reference.

Therefore, if the pins are tied together, the UV hysteresis is 100 mV.

The hysteresis can be adjusted by placing a resistor between

UVL and UVH.

Figure 51 illustrates the positive voltage monitoring input

connection. An external resistor network divides the supply

voltage for monitoring. An undervoltage event is detected when

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