LTM9002 datasheet(21/34 Pages) LINER

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21576514fa

LTC2157-14/

LTC2156-14/LTC2155-14

APPLICATIONS INFORMATION

Programmable LVDS Output Current

The default output driver current is 3.5mA. This current

can be adjusted by serially programming mode control

1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.

Optional LVDS Driver Internal Termination

In most cases, using just an external 100Ω termination

resistor will give excellent LVDS signal integrity. In addi-

tion, an optional internal 100Ω termination resistor can

be enabled by serially programming mode control register

A3. The internal termination helps absorb any reflections

caused by imperfect termination at the receiver. When the

internal termination is enabled, the output driver current

is doubled to maintain the same output voltage swing.

Overflow Bit

The overflow output bit (OF) outputs a logic high when

the analog input is either overranged or underranged. The

overflow bit has the same pipeline latency as the data bits.

The OF output is double data rate; when CLKOUT+ is low,

channel A’s overflow is available; when CLKOUT+ is high,

channel B’s overflow is available.

Phase Shifting the Output Clock

To allow adequate set-up and hold time when latching the

output data, the CLKOUT+ signal may need to be phase

shifted relative to the data output bits. Most FPGAs have

this feature; this is generally the best place to adjust the

timing.

Alternatively, the ADC can also phase shift the CLKOUT+/

CLKOUT– signals by serially programming mode control

90°, or 135°. To use the phase shifting feature the clock

duty cycle stabilizer must be turned on. Another con-

trol register bit can invert the polarity of CLKOUT+ and

CLKOUT–, independently of the phase shift. The combina-

tion of these two features enables phase shifts of 45° up

to 315° (Figure 11).

Figure 11. Phase Shifting CLKOUT

CLKOUT+

D0-D13, OF

PHASE

SHIFT

0°

45°

90°

135°

180°

225°

270°

315°

CLKINV

CLKPHASE1

MODE CONTROL BITS

CLKPHASE0

21576514 F11

ENC+

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