LTC4099 datasheet(22/52 Pages) LINER

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LTC4155

4155fc

WALLSNS pins. The voltage threshold values previously

listed and specified in the Electrical Characteristics table

are valid when each input is connected to its respective

sense pin through a 3.6k resistor.

The status of the USB and WALL inputs is monitored

continuously and reported by I2C, with the option of

generating several interrupts. When all three conditions

previously listed are true, the LTC4155 will report the input

valid by asserting USBSNSGD or WALLSNSGD in the I2C

port. Optionally, if external power interrupts are enabled,

an interrupt request will be generated.

When power is applied simultaneously to both inputs,

the LTC4155 will draw power from the WALL input by

default. If the I2C PRIORITY bit is asserted, the LTC4155

will instead draw power from the USB input when both

inputs are present. The USB On-The-Go step-up regulator

delivers power only to the USB input, and the PRIOR-

ITY bit is ignored in this mode. The input current limits

USBILIM[4:0] and WALLILIM[4:0] also reset to 100mA

default mode under different criteria. In all other respects,

the two inputs are identical.

An optional capacitor may be placed between the OVGCAP

pin and GND to minimize input current disruption when

switching from one input to the other while operating at

high power levels. The capacitor must be rated to withstand

at least 13V and should be approximately ten times larger

than the total gate capacitance of the series NMOS power

transistors. Capacitance on this pin can also be used to

slow the gate charging if the application requires controlled

inrush current to any additional input capacitance on the

VBUS pin. If fast switching between input or inrush control

is not necessary, OVGCAP may be left unconnected.

If overvoltage protection is not necessary in the application,

connect USBSNS to VBUS with a 3.6k resistor, as shown

in Figure 3. If the USB On-The-Go step-up regulator is

not used in the application, it is also possible to connect

WALLSNS to VBUS through 3.6k and leave USBSNS open.

100mA Linear Battery Charger Mode

The LTC4155 features a mode to support USB low power

operation. Total input current to the LTC4155 is guaranteed

to remain below 100mA in this mode when the recom-

mended resistor is used on the CLPROG2 pin. The step-

down switching regulator does not operate in this mode.

Instead, a linear regulator provides power from VBUS to

VOUT and the battery. The linear battery charger follows

the same constant-current/constant-voltage algorithm as

the switching regulator, but regulates input current rather

than battery charge current. The voltage on the CLPROG2

pin represents the input current in this mode, using the

expression:

IVBUS =

VCLPROG2

RCLPROG2

•80

()

Battery charge current is represented by the voltage on

the PROG pin, but it is not regulated in this mode.

ICHARGE =

VPROG

RPROG

• 1000

()

VOUTwillgenerallybeveryclosetothebatteryvoltagewhen

the battery charger is enabled, except when the battery

voltage is very low, the LTC4155 will increase the imped-

ance between VOUT and BATSNS to facilitate instant-on

operation. If the system load plus battery charge current

exceeds the available input current, battery charge current

will be sacrificed to give priority to the load. If the system

load alone exceeds the available input current, VOUT must

fall to the battery voltage so that the battery may provide

the supplemental current.

The battery will charge to the float voltage specified by

the I2C setting VFLOAT[1:0]. See Table 12.

When the battery charger is disabled or terminated, VOUT

will be regulated to 4.35V.

OPERATION

VBUS

TO POWER

INPUT

OVGCAP

USBGT

USBSNS

WALLGT

LTC4155

WALLSNS

4155 F03

Figure 3. No Overvoltage Protection

LTC4099 Datasheet(PDF) 22 Page - Linear Technology

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