LTC4099 datasheet(26/52 Pages) LINER

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LTC4155

4155fc

subsequent bus read operations. The sub address pointer

the SMBus write byte and read byte protocols explained

in detail under the SMBus Protocol Compatibility section.

Bus Write Operation

The bus master initiates communication with the LTC4155

with a START condition and the LTC4155’s write address.

If the address matches that of the LTC4155, the LTC4155

returns an acknowledge. The bus master should then deliver

the sub address. The sub address value is transferred to a

special pointer register within the LTC4155 upon the return

of the sub address acknowledge bit by the LTC4155. If the

master wishes to continue the write transaction, it may

then deliver the data byte. The data byte is transferred

to an internal pending data register at the location of the

sub address pointer when the LTC4155 acknowledges the

data byte. The LTC4155 is then ready to receive a new sub

address, optionally repeating the [SUB ADDRESS][DATA]

cycle indefinitely. After the write address, the odd position

bytes always represent a sub address pointer assignment

and the even position bytes always represent data to

be stored at the location referenced by the sub address

pointer. The master may terminate communication with

the LTC4155 after any even or odd number of bytes with

either a repeat START or a STOP condition. If a repeat

START condition is initiated by the master, the LTC4155,

or any other chip on the I2C bus, can then be addressed.

The LTC4155 will remember, but not act on, the last input

of valid data that it received at each sub address location.

This cycle can also continue indefinitely. Once all chips

on the bus have been addressed and sent valid data, a

global STOP can be sent and the LTC4155 will immediately

update all of its command registers with the most recent

pending data that it had previously received. This delayed

execution behavior is compliant with the PMBus group

command protocol.

Bus Read Operation

The LTC4155 contains seven readable registers. Three

are read only and contain status information. Four contain

control information which may be both written and read

back by the bus master.

Only one of the seven sub addressed data registers is ac-

cessible during each bus read operation. The data returned

by the LTC4155 is from the data register pointed to by the

contents of the sub address pointer register. The pointer

ous bus write operation.

In preparation for a bus read operation, it may be ad-

vantageous for a bus master to prematurely terminate a

write transaction with a STOP or repeat START condition

after transmitting only an odd number of bytes. The last

transmitted byte then represents a pointer to the register

of interest for the subsequent bus read operation.

The bus master reads status data from the LTC4155

with a START or repeat START condition followed by the

LTC4155 read address. If the read address matches that

of the LTC4155, the LTC4155 returns an acknowledge.

Following the acknowledgement of its read address, the

LTC4155 returns one bit of status information for each of

the next eight clock cycles from the register selected by

the sub address pointer. Additional clock cycles from the

master after the single data byte has been read will leave

the SDA line high (0xFF transmitted). The LTC4155 will

never acknowledge any bytes during a bus read operation

with the exception of its read address.

To read the same register again, the transaction may be

repeated starting with a START followed by the LTC4155

read address. It is not necessary to rewrite the sub address

pointer register if the sub address has not changed. To read

a different register, a write transaction must be initiated

with a START or repeat START followed by the LTC4155

write address and sub address pointer byte before the

read transaction may be repeated.

When the contents of the sub address pointer register

point to a writeable command register, the data returned

in a bus read operation is the pending command data at

that location if it had been modified since the last STOP

condition. After a STOP condition, all pending data is

copied to the command registers for immediate effect. The

contents of several writeable registers within the LTC4155

are modified upon removal of input power without an I2C

transaction. USBILIM[4:0] and WALLILIM[4:0] default

to either 100mA mode (0x00) or CLPROG1 mode (0x1F)

OPERATION

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