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LTC4155

4155fc

Byte Format

Each frame sent to or received from the LTC4155 must

be eight bits long, followed by an extra clock cycle for the

acknowledge bit. The data should be sent to the LTC4155

most significant bit (MSB) first.

Master and Slave Transmitters and Receivers

Devices connected to an I2C bus may be classified as

either master or slave. A typical bus is composed of one

or more master devices and a number of slave devices.

Some devices are capable of acting as either a master or

a slave, but they may not change roles while a transaction

is in progress.

The transmitter/receiver relationship is distinct from that

of master and slave. The transmitter is responsible for

control of the SDA line during the eight bit data portion

of each frame. The receiver is responsible for control of

SDA during the ninth and final acknowledge clock cycle

of each frame.

All transactions are initiated by the master with a START

or repeat START condition. The master controls the active

(falling) edge of each clock pulse on SCL, regardless of its

status as transmitter or receiver. The slave device never

brings SCL LOW, but may extend the SCL LOW time to

implement clock stretching if necessary. The LTC4155

does not clock stretch and will never hold SCL LOW under

any circumstance.

The master device begins each I2C transaction as the

transmitter and the slave device begins each transaction

as the receiver. For bus write operations, the master acts

as the transmitter and the slave acts as receiver for the

duration of the transaction. For bus read operations, the

master and slave exchange transmit/receive roles following

the address frame for the remainder of the transaction.

Acknowledge

The acknowledge signal (ACK) is used for handshaking

between the transmitter and receiver. When the LTC4155

is written to, it acknowledges its write address as well as

the subsequent data bytes as a slave receiver. When it is

read from, the LTC4155 acknowledges its read address

as a slave receiver. The LTC4155 then changes to a slave

transmitter and the master receiver may optionally acknowl-

edge receipt of the following data byte from the LTC4155.

The acknowledge related clock pulse is always generated by

the bus master. The transmitter (master or slave) releases

the SDA line (HIGH) during the acknowledge clock cycle.

The receiver (slave or master) pulls down the SDA line

during the acknowledge clock pulse so that it is a stable

LOW during the HIGH period of this clock pulse.

When the LTC4155 is read from, it releases the SDA line

after the eighth data bit so that the master may acknowl-

edge receipt of the data. The I2C specification calls for a

not acknowledge (NACK) by the master receiver following

the last data byte during a read transaction. Upon receipt

of the NACK, the slave transmitter is instructed to release

control of the bus. Because the LTC4155 only transmits

one byte of data under any circumstance, a master ac-

knowledging or not acknowledging the data sent by the

LTC4155 has no consequence. The LTC4155 will release

the bus in either case.

Slave Address

The LTC4155 responds to a 7-bit address which has been

factory programmed to 0b0001_001[R/W]. The LSB of

the address byte, known as the read/write bit, should be

0 when writing data to the LTC4155, and 1 when reading

data from it. Considering the address an 8-bit word, then

the write address is 0x12, and the read address is 0x13.

The LTC4155 will acknowledge both its read and write

addresses.

Sub Addressed Access

The LTC4155 has four command registers for control

input and three status registers for status reporting. They

are accessed by the I2C port via a sub addressed pointer

system where each sub address value points to one of

the seven control or status registers within the LTC4155.

The sub address pointer is always the first byte written

immediately following the LTC4155 write address dur-

ing bus write operations. The sub address pointer value

persists after the bus write operation and will determine

which data byte is returned by the LTC4155 during any

OPERATION

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