SLWS131 datasheet(23/37 Pages) TI1

23 / 37 page

GRAYCHIP, INC.

- 21 -

JUNE 22, 1998

GC3021 MIXER AND CARRIER REMOVAL CHIP

DATA SHEET

This document contains information which may be changed at any time without notice

4.8

SNAPSHOT CONTROL REGISTER

Registers 12 controls the snapshot memory. The suggested default is 0002 (HEX).

ADDRESS 12:

SNAP_REG

BIT

TYPE

NAME

DESCRIPTION

0,1 (LSB)

R/W

TRIGGER

This control sets the trigger condition which will start a

snapshot once the ARMED bit is set. The trigger

conditions are to start:

TRIGGER

DESCRIPTION

immediately,

when the SN strobe is received,

when the SNAP_SYNC is received

(See Section 4.2),

never

R/W

ARMED

The user sets this bit to arm the snapshot memory

so that it will start on the next trigger condition. The

chip clears this bit when the trigger occurs.

R/W

DONE

This bit goes high when the snapshot is complete.

4,5

R/W

SNAP_RATE

Determines the rate at which samples are stored

according to:

SNAP_RATE

DESCRIPTION

every clock, full rate samples

every other clock, half rate samples

every 3rd clock, third rate samples

every 4th clock, quarter rate samples.

6,7

R/W

unused

8-15 (MSB)

R/W

SNAP_DELAY

Delay from snapshot trigger until the start of snapshot.

The delay is:

SNAP_DELAY*(SNAP_RATE+1)

clock cycles where SNAP_DELAY ranges from 0 to 255.

4.9

PHASE REGISTER

See PHASE_HOLD in Section 4.5.

4.10

ONE SHOT ADDRESS

The one shot pulse is generated on the OS pin by writing to address 14. This is a write-only address.

The data written to it is irrelevant.

4.11

TEST OUTPUT REGISTER

status (bit 1). The status bit is high if the internal 1 kHz clock is being used by the chip.

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