GRAYCHIP, INC.

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JUNE 22, 1998

GC3021 MIXER AND CARRIER REMOVAL CHIP

DATA SHEET

This document contains information which may be changed at any time without notice

DSP chip) can write into a register by setting A[0:8] to the desired register address, setting the R/W pin low,

setting C[0:15] to the desired value and then pulsing CS low.

To read from a control register the processor must set A[0:8] to the desired address, set R/W high,

and then set CS low. The chip will then drive C[0:15] with the contents of the selected register. After the

processor has read the value from C[0:15] it should set CS high. The C[0:15] pins are turned off (high

impedance) whenever CS is high or R/W is low. The chip will only drive these pins when CS is low and R/W

is high.

The chip’s control address space is divided into fourteen control registers, a test port, four DC offset

registers, 256 phase error memory words, and 256 snapshot memory words. The 14 control registers are

MODE_REG, SYNC_REG0, SYNC_REG1, DELAY_REG, COUNTER_REG, PLL_REG, FREQ_REG0,

FREQ_REG1, OUTPUT_REGA, OUTPUT_REGB, OUTPUT_REGC, OUTPUT_REGD, SNAP_REG, and

PHASE_REG. The control registers are mapped to addresses 0 to 13. See Section 4.0 for details about the

contents of these registers.

Address 14 is used to generate a one-shot pulse. This pulse, OS, which is one clock cycle wide,

can be output from the chip on the SO pin or used to synchronize internal circuits. Address 15 is a read only

port used to monitor the power-down and keepalive clock functions for test. Addresses 16 through 19 are

the DC offset registers DC_I_IN, DC_Q_IN, DC_I_OUT, DC_Q_OUT.

Addresses 20 through 255 are unused.

Addresses 256 through 511 are shared between the phase error memory and the snapshot

memory. Reading from these addresses accesses the contents of the snapshot memory. Writing to these

addresses loads the phase error lookup memory.

2.2

SYNC COUNTER

The sync counter circuit is used to generate sync pulses for the chip. The circuit accepts two sync

inputs (SA and SB) and generates internal syncs and a sync out (SO) pulse. The circuit contains a 20 bit

The counter’s terminal count (TC) can be used as a synchronization pulse. The lower 12 bits from the

counter are used as input data during diagnostics.

The circuit can generate a one-shot pulse (OS) which can be used as a synchronization pulse.

The input syncs SA and SB can be delayed by up to 258 clock cycles. The delayed syncs (DSA and

DSB) can be used to adjust the sync timing to meet system requirements.

The internal syncs are used to synchronize the counter, the symbol align circuit, the snapshot

memory, the phase lock loop circuit and NCO circuit. Each circuit can be independently synchronized to SA,

SB, DSA, DSB, TC, OS, or left to free run. The sync output can also be chosen from these syncs.

2.3

CLOCK GENERATOR

The clock generator generates the internal clocks from the clock input (CK). Two clock enable

inputs (CKENA and CKENB) are used to enable or disable the clock. Both enables must be low for internal

clocks to be generated. The enables are clocked into the chip and are used to enable or disable the