 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
WM8311 Datasheet(PDF) 301 Page - Wolfson Microelectronics plc |
|
|
|||||||||||||||||||||||||||||
WM8311 Datasheet(HTML) 301 Page - Wolfson Microelectronics plc |
|
|
301 / 302 page  Pre-Production WM8311 w PP, May 2012, Rev 3.1 301 33 REVISION HISTORY DATE REV DESCRIPTION OF CHANGES CHANGED BY 18/02/10 3.1 Updated definition of DCn_SOFT_START registers RST_DUR description updated Updated description of AUX_CVT_ENA and TCH_CVT_ENA, noting that measurement data is not available until the associated interrupt is set. AUXADC input impedance corrected to 400kohm. PH 24/06/10 3.1 Amended LDO12 current capability to 2mA. Amended LDO13 current capability to 20mA DC4 maximum current spec restored to 90mA. DC4 Elec Chars updated to include 90mA for Vload ≤ 8V. DC4_RANGE updated to support Vout >= 6.5V only. Amended Test Conditions for LDO4, 5 to be same as others. Clarified (in Section 13) the 32.768kHz GPIO output only supported in OFF state if the selected power domain remains on. Clarified (in Section 21) the External Power Clock is controlled in the power sequences via EPE1 or EPE2. Updated wording and terminology, making consistent with other PMIC datasheets. Review input from WM8321 incorporated as applicable. DORW replaced with DCRW. DBE replaced with InstantConfig™ EEPROM (ICE). Added SDOUT1 pull-up requirement. Typical connections drawing updated to show XOSCGND close to XTI/XTO pins and to include DC-DC output capacitors. PH 22/07/10 3.1 Noted maximum output capacitance for LDO7 (4.7uF). Updates regarding Battery Charger Interrupts preventing SLEEP transitions - CHG_START_EINT must be cleared first. Clarification added to CLKOUT function when XTAL_INH=1. DBVDD1, DBVDD2 domains merged into DBVDD. PVDD1, PVDD2 domains merged into PVDD. Watchdog description updated wrt Device Reset response. SDOUT1 description updated as an Open Drain output, with pull-up resistor required. “Register Map by Address” section updated. Default value of PWRSTATE_DLY corrected. PH 24/11/10 3.1 CE000609 errata added (OTP Command End Interrupt) CE000610 errata added (DC3 quiescent current in LDO mode) CE000611 errata added (Power Sequence in failure conditions) CE000613 errata added (DC4 Hardware Control) CE000614 errata added (FLL Register readback) CE000649 errata added (Watchdog timeout) PH 3/12/10 3.1 Undervoltage margin specified for DC-DC converters 1,2,3. Overvoltage margin specified for DC-DC converters 1,2. Chip Temperature (AUX_DATA) equation updated. NTCBIAS voltage added to Electrical Characteristics. PH 7/3/11 3.1 RTC_PINT_FREQ definition updated. Added notes that SLEEP > OFF is not a controlled transition; converters and regulators are disabled immediately. RESET pin description updated to note integrated pull-up. IRQ description updated to note pull-up in Open Drain mode. System Reset and Device Reset descriptions updated, consistent with the Summary Table. Recommended external pull-up resistances added in Pin Description. Internal pull-up / pull-down resistances added in Electrical Characteristics. CE000612 errata added (GPn_POL in development mode) PH |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
