RT5002

15

DS5002-00

November 2011

www.richtek.com

Note 1. Stresses listed as the above

"Absolute Maximum Ratings" may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended

periods may remain possibility to affect device reliability.

Note 2. Guaranteed by design.

Note 3.

JEDEC 51-7 thermal measurement standard. The measurement case position of

package.

Note 4. Devices are ESD sensitive. Handling precaution is recommended.

Note 5. The device is not guaranteed to function outside its operating conditions.

°C, unless otherwise specified)

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Logic Inputs (SDA SCL)

Logic-High

2.0

--

--

SDA, SCL Input

Threshold Voltage

Logic-Low

--

--

0.8

V

I

2

C Timing Characteristics

SCL Clock Rate

--

--

400

kHz

Hold Time (Repeated) START

Condition. After this period, the

first clock pulse is generated

0.6

--

--

μs

LOW Period of SCL Clock

1.3

--

--

μs

HIGH Period of SCL Clock

0.6

--

--

μs

Set-up Time for Repeated START

Condition

0.6

--

--

μs

Data Hold Time

0

--

0.9

μs

Data Set-up Time

100

--

--

ns

Set-up Time for STOP Condition

0.6

--

--

μs

Bus Free Time between a STOP

and START Condition

1.3

--

--

μs

Rise Time of both SDA and SCL

Signals

20

--

300

ns

Fall Time of both SDA and SCL

Signals

20

--

300

ns

SDA and SCL Output Low Sink

Current

SDA or SCL Voltage = 0.4V

2

--

--

mA