AD1845

–24–

REV. C

LLM

Left Line Mute. Setting this bit to 1 mutes the left line input into the output mixer.

This register’s initial state after reset is “1xx0 1000.”

Right Line Gain, Attenuate, Mute, Mix Register (IXA3:0 = 19)

IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

19

RLM

res

res

RLG4

RLG3

RLG2

RLG1

RLG0

RLG4:0

Right Line Mix Gain. Allows setting the right line mix gain in thirty-two 1.5 dB steps. See Figure 10 for mix

gain level setting.

res

Reserved for future expansion. Always write zeros to these bits.

RLM

Right Line Mute. Setting this bit to 1 mutes the right line input into the output mixer.

This register’s initial state after reset is “1xx0 1000.”

A4/G4

A3/G3

A2/G2

A1/G1

A0/G0

Mix Gain

0

0

0

0

0

+12.0 dB

0

0

0

0

1

+10.5 dB

0

0

0

1

0

+9.0 dB

0

0

0

1

1

+7.5 dB

0

0

1

0

0

+6.0 dB

0

0

1

0

1

+4.5 dB

0

0

1

1

0

+3.0 dB

0

0

1

1

1

+1.5 dB

0

1

0

0

0

+0.0 dB

0

1

0

0

1

–1.5 dB

0

1

0

1

0

–3.0 dB

0

1

0

1

1

–4.5 dB

0

1

1

0

0

–6.0 dB

0

1

1

0

1

–7.5 dB

0

1

1

1

0

–9.0 dB

0

1

1

1

1

–10.5 dB

1

0

0

0

0

–12.0 dB

1

0

0

0

1

–13.5 dB

1

0

0

1

0

–15.0 dB

1

0

0

1

1

–16.5 dB

1

0

1

0

0

–18.0 dB

1

0

1

0

1

–19.5 dB

1

0

1

1

0

–21.0 dB

1

0

1

1

1

–22.5 dB

1

1

0

0

0

–24.0 dB

1

1

0

0

1

–25.5 dB

1

1

0

1

0

–27.0 dB

1

1

0

1

1

–28.5 dB

1

1

1

0

0

–30.0 dB

1

1

1

0

1

–31.5 dB

1

1

1

1

0

–33.0 dB

1

1

1

1

1

–34.5 dB

Figure 10. Mix Gain Level Setting: AUX1, AUX2, MIC and LINE

Lower Timer Bits Register (IXA3:0 = 20)

IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

20

TL7

TL6

TL5

TL4

TL3

TL2

TL1

TL0

TL7:0

Lower Timer Bits. This byte is the lower byte of the timer register containing the eight least significant bits of the

16-bit register. Reads from this register return the same value which was written. The current timer value con-

tained in the counters cannot be read.

This register’s initial state after reset is “0000 0000.”