AD1845

–25–

REV. C

Upper Timer Bits Register (IXA3:0 = 21)

IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

21

TU7

TU6

TU5

TU4

TU3

TU2

TU1

TU0

TU7:0

Upper Timer Bits. This byte is the upper byte of the timer register containing the eight most significant bits of the

16-bit register. Reads from this register return the same value which was written. The current timer value con-

tained in the counters cannot be read. The timer counter is determined by the clock source selected (see below).

Input Frequency

Divider

Timer Counter

24.576 MHz

247

10.050

µs

14.31818 MHz

144

10.057

µs

24.000 MHz

242

10.083

µs

25.000 MHz

252

10.080

µs

33.000 MHz

333

10.091

µs

This register’s initial state after reset is “0000 0000.”

Upper Frequency Select Bits Register (IXA3:0 = 22)

IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

22

FU7

FU6

FU5

FU4

FU3

FU2

FU1

FU0

FU7:0

Upper Frequency Select Bits. This register is accessible when FREN is 1. Writing to this register allows the user

to program the sampling frequency from 4 kHz to 50 kHz in 1 Hz increments. Writing to the Lower and Upper

Frequency Select Register allows the AD1845 to process audio data using approximately 50,000 different audio

sample rates. One LSB represents exactly one hertz. Selecting frequencies below 4 kHz or above 50 kHz will

result in degraded audio performance. Some common sample rates are listed below:

Quality

Sampling Frequency

FU7:0 (hex)

FL7:0 (hex)

Voice

8.0 kHz

0001 1111

0100 0000

default

Radio

11.025 kHz

0010 1011

0001 0001

Tape

22.05 kHz

0101 0110

0010 0010

CD

44.1 kHz

1010 1100

0100 0100

DAT

48.0 kHz

1011 1011

1000 0000

This register’s initial state after reset is “0001 1111.”

Lower Frequency Select Bits Register (IXA3:0 = 23)

IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

23

FL7

FL6

FL5

FL4

FL3

FL2

FL1

FL0

FL7:0

Lower Frequency Select Bits. Writing to the Lower Frequency Select register updates the entire 16-bit frequency register.

This register’s initial state after reset is “0100 0000.”

Capture Playback Timer Register (IXA3:0 = 24)

IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

24

res

TI

CI

PI

CU

CO

PO

PU

PU

Playback Underrun. This bit is set when the DAC runs out of data and a sample has been missed.

PO

Playback Overrun. This bit is set when the host tries to write data into the FIFO and the write was ignored be-

cause the FIFO was full.

CO

Capture Overrun. This bit is set when the ADC has a sample to load into the FIFO, and the data was ignored

because the capture FIFO was full.

CU

Capture Underrun. This bit is set when the host attempts to read from the capture FIFO when it is empty. Under

these circumstances, the last valid byte is sent to the host.

PI

Playback Interrupt. This bit indicates that there is an interrupt pending from the playback DMA count registers.

CI

Capture Interrupt. This bit indicates that there is an interrupt pending from the capture DMA count registers.