AD1845

–28–

REV. C

XFS2:0

Crystal/Clock Input Frequency Select. On power up or reset, the AD1845 expects a 24.576 MHz input clock. If

the clock source connected to the AD1845 is different from the default condition, then the clock input must be

selected using this register. For a detailed explanation see the Power Up and Reset section of the data sheet. Figure

13 summarizes the valid input clock frequencies. Clock sources with excessive jitter may not yield optimal analog

performance.

This register’s initial state after reset is “000x xxx0.”

XFS2

XFS1

XFS0

Input Frequency

0

0

0

24.576

MHz

0

0

1

14.31818 MHz

0

1

0

24.000

MHz

0

1

1

25.000

MHz

1

0

0

33.000

MHz

1

0

1

Reserved

1

1

0

Reserved

1

1

1

Reserved

Figure 13. Input Frequency Selection

Capture Upper Base Count Register (IXA3:0 = 30)

IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

30

CUB7

CUB6

CUB5

CUB4

CUB3

CUB2

CUB1

CUB0

CUB7:0

Capture Upper Base Count. This byte is the upper byte of the base count register containing the eight most sig-

nificant bits of the second 16-bit base register. Reads from this register return the same value that was written.

The current count contained in the counters cannot be read.

This register’s initial state after reset is “0000 0000.”

Capture Lower Base Count Register (IXA3:0 = 31)

IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

31

CLB7

CLB6

CLB5

CLB4

CLB3

CLB2

CLB1

CLB0

CLB7:0

Capture Lower Base Count. This byte is the lower byte of the base count register containing the eight least signifi-

cant bits of the second 16-bit base register. Reads from this register return the same value that was written. The

current count contained in the counters cannot be read.

This register’s initial state after reset is “0000 0000.”