AD1845 datasheet(30/40 Pages) AD

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AD1845

–30–

REV. C

is activated when both Playback Enable (PEN) is set and Play-

back PIO (PPIO) is set. Capture PIO is activated when both

Capture Enable (CEN) is set and Capture PIO (CPIO) is set.

See Figures 20 and 21 for the detailed timing of the control

RD and WR signals are used to

define the actual read and write cycles, respectively. The host

holds

CS LO during these transfers. The DMA Capture Data

Acknowledge (

CDAK) and Playback Data Acknowledge

(

PDAK) must be held inactive, i.e., HI.

For read/capture cycles, the AD1845 will place data on the

DATA7:0 lines while the host is asserting the read strobe,

RD,

by holding it LO. For write/playback, the host must place data

on the DATA7:0 pins while strobing the

WR signal LO. The

AD1845 latches the write/playback data on the rising edge of

the

WR strobe.

When using PIO data transfers, the Status Register must be

polled to determine when data should be transferred. Note that

the ADC capture data will be ready (CRDY HI) from the previ-

ous sample period shortly before the DAC playback data is

ready (PRDY HI) for the next sample period. The user should

not wait for both ADCs and DACs to become ready before

initiating data transfers. Instead, as soon as capture data is

ready, it should be read; as soon as the DACs are ready, play-

back data should be written.

Values written to the XCTL1:0 bits in the Pin Control Register

(IXA3:0 = 10) will be reflected in the state of the XCTL1:0

external output pins. This feature allows a simple method for

signaling or software control of external logic. Changes in state

of the external XCTL pins will occur within one sample period.

Because their change is referenced to the internal sample clock,

no useful timing diagram can be constructed.

DIRECT MEMORY ACCESS (DMA) TRANSFERS

The second type of bus cycle supported by the AD1845 are

DMA transfers. Both dual channel and single channel DMA

operations are supported. To enable Playback DMA transfers,

playback enable (PEN) must be set and PPIO cleared. To

enable Capture DMA transfers, capture enable (CEN) must be

set and CPIO cleared. During DMA transfers, the AD1845

asserts HI the Capture Data Request (CDRQ) or the Playback

Data Request (PDRQ) followed by the host’s asserting LO

the DMA Capture Data Acknowledge (

CDAK) or Playback

Data Acknowledge (

PDAK), respectively. The host’s asserted

CDRQ/PDRQ

OUTPUTS

tADSU

tADHD

tDHD1

tRDDV

tSTW

tDBDL

tCSSU

tCSHD

tSUDK1

tSUDK2

CDAK INPUT

CS INPUT

DBEN & DBDIR

OUTPUTS

RD INPUT

DATA7:0

OUTPUTS

DATA1:0

INPUTS

Figure 20. Control Register/PIO Read Cycle

CDRQ/PDRQ

OUTPUTS

tADSU

tADHD

tDHD2

tDBDL

tCSSU

tCSHD

PDAK INPUT

CS INPUT

DBEN OUTPUT

WR INPUT

DATA7:0

INPUTS

DATA1:0

INPUTS

tWDSU

DBDIR OUTPUT

tSUDK2

tSTW

tSUDK1

Figure 21. Control Register/PIO Write Cycle

Acknowledge signals cause the AD1845 to perform DMA trans-

fers. The input address lines, ADR1:0, are ignored. Data is

transferred between the proper internal sample registers.

The read strobe (

RD) and write strobe (WR) delimit valid data

for DMA transfers. Chip select (

CS) is a “don’t care”; its state

is ignored by the AD1845.

The AD1845 may assert the Data Request signals, CDRQ and

PDRQ, at any time. Once asserted, these signals will remain

active HI until the corresponding DMA cycle occurs with the

host’s Data Acknowledge signals. The Data Request signals will

be deasserted after the falling edge of the final

RD or WR strobe

in the transfer of a sample, which typically consists of multiple

bytes. See “Data Ordering” above for a definition of “sample.”

DMA transfers may be independently aborted by resetting the

Capture Enable (CEN) and/or Playback Enable (PEN) bits in

the Interface Configuration Register. The current capture

sample transfer will be completed if a capture DMA is termi-

nated. The current playback sample transfer must be completed

if a playback DMA is terminated. If CDRQ and/or PDRQ are

asserted HI while the host is resetting CEN and/or PEN, the

request must be acknowledged. The host must assert

CDAK

and/or

PDAK LO and complete a final sample transfer.

Single-Channel DMA

Single-Channel DMA mode allows the AD1845 to be used in

systems with only a single DMA channel. It is enabled by set-

ting the SDC bit in the Interface Configuration Register. All

captures and playbacks take place on the playback channel.

Obviously, the AD1845 cannot perform a simultaneous capture

and playback in Single-Channel DMA mode.

Playback will occur in Single-Channel DMA mode exactly as it

does in Two-Channel mode. Capture, however, is diverted to

the playback channel which means that the capture data request

occurs on the PDRQ pin and the capture data acknowledge

must be received on the

PDAK pin. The CDRQ pin will re-

main inactive LO. Any inputs to

CDAK will be ignored.

Playback and capture are distinguished in Single-Channel DMA

mode by the state of the playback enable (PEN) or capture

enable (CEN) control bits. If both PEN and CEN are set in

Single-Channel DMA mode, playback will be presumed.

To avoid confusion of the origin of a request when switching

between playback and capture in Single-Channel DMA mode,

both CEN and PEN should be disabled and all pending re-

quests serviced before enabling the alternative enable bit.

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