AD1845

–26–

REV. C

TI

Timer Interrupt. This bit indicates that there is an interrupt pending from the timer count registers.

res

Reserved for future expansion. Always write zero to this bit.

Playback, Capture and timer interrupts may be cleared simultaneously by writing to the Status Register. These interrupts may be

cleared individually by writing a “0” to the corresponding bit. Note that the timer interrupt requires a minimum wait period of 10

µs

after the interrupt is set and before TI is recognized. Use TE to clear the timer interrupt immediately.

This register’s initial state after reset is “100x x000.”

Revision ID Register (IXA3:0 = 25)

IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

25

V2

V1

V0

res

res

CID2

CID1

CID0

V2:0

Version Number. Indicates the version of the AD1845.

res

Reserved for future expansion. Always write zeros to these bits.

CID2:0

Chip ID Number.

This register’s initial state after reset is “x000 0000.”

Mono Control Registers (IXA3:0 = 26)

IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

26

MIM

MOM

res

res

MIA3

MIA2

MIA1

MIA0

MIA3:0

Mono Input Attenuation. The least significant bit represents 3.0 dB attenuation. See Figure 11 to determine

the attenuation.

res

Reserved for future expansion. Always write zeros to these bits.

MOM

Mono Output Mute. M_OUT is muted by setting MOM to 1.

0

Mono output not muted

1

Mono output muted

MIM

Mono Input Mute. M_IN is muted by setting MIM to 1.

0

Mono input not muted

1

Mono input muted

This register’s initial state after reset is “00xx 0011.”

MIA3

MIA2

MIA1

MIA0

MONO Attenuation

0

0

0

0

0.0 dB

0

0

0

1

–3.0 dB

0

0

1

0

–6.0 dB

0

0

1

1

–9.0 dB

0

1

0

0

–12.0 dB

0

1

0

1

–15.0 dB

0

1

1

0

–18.0 dB

0

1

1

1

–21.0 dB

1

0

0

0

–24.0 dB

1

0

0

1

–27.0 dB

1

0

1

0

–30.0 dB

1

0

1

1

–33.0 dB

1

1

0

0

–36.0 dB

1

1

0

1

–39.0 dB

1

1

1

0

–42.0 dB

1

1

1

1

–45.0 dB

Figure 11. Mono Attenuation