AD1845 datasheet(29/40 Pages) AD

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AD1845

–29–

REV. C

DATA AND CONTROL TRANSFERS

The AD1845 SoundPort Stereo Codec supports a DMA re-

quest/grant architecture for transferring data with the host com-

puter bus. One or two DMA channels can be supported.

Programmed I/O (PIO) mode is also supported for control

PIO transfers can be made on one channel while the other is

performing DMA. Transfers to and from the AD1845

SoundPort Codec are asynchronous relative to the internal data

conversion clock. Transfers are buffered by FIFOs located in

the capture and playback paths.

Data Ordering

The number of byte-wide transfers required depends on the

data format selected. The AD1845 is designed for “little and

big endian” formats. In little endian format, the least significant

byte (i.e., occupying the lowest memory address) gets trans-

ferred first. Therefore, 16-bit data transfers require first trans-

ferring the least significant bits [7:0] and then transferring the

most significant bits [15:8], where Bit 15 is the most significant

bit in the word. In big endian format, byte ordering for the most

significant (MS) byte and least significant (LS) byte are swapped.

In addition, left channel data is always transferred before right

channel data with the AD1845. The following figures should

make these requirements clear.

SAMPLE 6

SAMPLE 5

SAMPLE 4

SAMPLE 3

SAMPLE 2

SAMPLE 1

BYTE 4

BYTE 3

BYTE 2

BYTE 1

TIME

MONO

Figure 14. 8-Bit Mono Data Stream Sequencing

BYTE 4

BYTE 3

BYTE 2

BYTE 1

TIME

SAMPLE 3

SAMPLE 2

SAMPLE 1

RIGHT

LEFT

RIGHT

LEFT

Figure 15. 8-Bit Stereo Data Stream Sequencing

BYTES 3 AND 4

BYTES 1 AND 2

SAMPLE 6

SAMPLE 5

SAMPLE 4

SAMPLE 3

SAMPLE 2

SAMPLE 1

TIME

Figure 16. 16-Bit Mono Data Stream Sequencing, Little

Endian

BYTES 3 AND 4

BYTES 1 AND 2

TIME

SAMPLE 3

SAMPLE 2

SAMPLE 1

RIGHT MS

RIGHT LS

LEFT MS

LEFT LS

Figure 17. 16-Bit Stereo Data Stream Sequencing, Little

Endian

BYTES 3 AND 4

BYTES 1 AND 2

TIME

SAMPLE 6 SAMPLE 5 SAMPLE 4

SAMPLE 4

SAMPLE 3

SAMPLE 2 SAMPLE 1

Figure 18. 16-Bit Mono Data Stream Sequencing, Big

Endian

BYTES 3 AND 4

BYTES 1 AND 2

TIME

SAMPLE 3

SAMPLE 2

SAMPLE 1

RIGHT LS

RIGHT MS

LEFT LS

LEFT MS

Figure 19. 16-Bit Stereo Data Stream Sequencing, Big

Endian

FIFO

The AD1845 includes two 16-sample deep FIFOs. The FIFOs

are built into the capture and playback paths and are completely

transparent to the user and require no programming. The

FIFOs are active in MODE1 and MODE2.

The AD1845 maintains a continuous playback stream by re-

questing data from the host until the FIFO located in the play-

back path is full. As the FIFO empties, new samples are

requested to keep the playback FIFO full. In the event that the

FIFO runs out of data and DACZ is reset to “0,” the last valid

sample will be continuously played back. If DACZ is “1,” the

AD1845 will output a midscale value.

The FIFO located in the capture data path attempts to stay

empty by making requests of the host every sample period that it

contains valid data. When the host system cannot respond

during the same sample period, the capture FIFO starts filling,

and avoids a loss of data in the audio data stream.

Data Bus Drivers

The AD1845 has built-in 8 or 16 mA bus drivers for interfacing

to the ISA bus. The drivers reduce the need for the off-chip

74_245 bus transceiver buffers in many applications. If higher

drive capability is required, 24 mA for example, the AD1845

generates the appropriate direction and enable signals. See

Figure 1 and refer to the Applications Circuits section of the

data sheet.

Control and Programmed I/O (PIO) Transfers

This simpler mode of transfers is used both for control register

accesses and programmed I/O. The 37 control and PIO data

registers cannot be accessed via DMA transfers. Playback PIO

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