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AD1895 Datasheet(PDF) 6 Page - Analog Devices

Part # AD1895
Description  192 kHz Stereo Asynchronous Sample Rate Converter
PDF  24 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD1895 Datasheet(HTML) 6 Page - Analog Devices

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REV. B
AD1895
–6–
PIN FUNCTION DESCRIPTIONS
Pin No.
IN/OUT (I/O)
Mnemonic
Description
1
IN
NC
No Connect
2
IN
MCLK_IN
Master Clock or Crystal Input
3
OUT
MCLK_OUT
Master Clock Output or Crystal Output
4
IN
SDATA_I
Input Serial Data (at Input Sample Rate)
5
IN/OUT
SCLK_I
Master/Slave Input Serial Bit Clock
6
IN/OUT
LRCLK_I
Master/Slave Input Left/Right Clock
7
IN
VDD_IO
3.3 V/5 V Input/Output Digital Supply Pin
8
IN
DGND
Digital Ground Pin
9
IN
BYPASS
ASRC Bypass Mode, Active High
10
IN
SMODE_IN_0
Input Port Serial Interface Mode Select Pin 0
11
IN
SMODE_IN_1
Input Port Serial Interface Mode Select Pin 1
12
IN
SMODE_IN_2
Input Port Serial Interface Mode Select Pin 2
13
IN
RESET
Reset Pin, Active Low
14
IN
MUTE_IN
Mute Input Pin—Active High Normally Connected to MUTE_OUT
15
OUT
MUTE_OUT
Output Mute Control—Active High
16
IN
WLNGTH_OUT_1
Hardware Selectable Output Wordlength—Select Pin 1
17
IN
WLNGTH_OUT_0
Hardware Selectable Output Wordlength—Select Pin 0
18
IN
SMODE_OUT_1
Output Port Serial Interface Mode Select Pin 1
19
IN
SMODE_OUT_0
Output Port Serial Interface Mode Select Pin 0
20
IN
TDM_IN
Serial Data Input
* (Only for Daisy-Chain Mode). Ground when not used.
21
IN
DGND
Digital Ground Pin
22
IN
VDD_CORE
3.3 V Digital Supply Pin
23
OUT
SDATA_O
Output Serial Data (at Output Sample Rate)
24
IN/OUT
LRCLK_O
Master/Slave Output Left/Right Clock
25
IN/OUT
SCLK_O
Master/Slave Output Serial Bit Clock
26
IN
MMODE_0
Master/Slave Clock Ratio Mode Select Pin 0
27
IN
MMODE_1
Master/Slave Clock Ratio Mode Select Pin 1
28
IN
MMODE_2
Master/Slave Clock Ratio Mode Select Pin 2
*Also used to input matched-phase mode data.
PIN CONFIGURATION
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD1895
TOP VIEW
(NOT TO SCALE
)
MUTE_IN
RESET
SMODE_IN_2
SMODE_IN_1
SMODE_IN_0
BYPASS
DGND
NC
MCLK_IN
MCLK_OUT
SDATA_I
VDD_IO
LRCLK_I
SCLK_I
MUTE_OUT
WLNGTH_OUT_1
WLNGTH_OUT_0
SMODE_OUT_1
SMODE_OUT_0
TDM_IN
DGND
MMODE_2
MMODE_1
MMODE_0
SCLK_O
VDD_CORE
SDATA_O
LRCLK_O
NC = NO CONNECT



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